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w88113c atapi cd-rom decoder & controller
w88113c data sheet revision history pages dates version version on web main contents 1 n/a 05/1998 0.50 first published 2 16,18,53,54, 56,61,64,67, 70,71,72,73, p86(add),91, 92,94,95,96 12/1998 0.60 for w88113c version f 3 1,5,14,21,46, 66 03/1999 0.61 text error fix 4 5 6 7 8 9 10 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
w88113c publication release date: mar. 1999 - i - revision 0.61 table of contents 1. overview ................................ ................................ ................................ ............. 1 1.1 features ................................ ................................ ................................ ................................ ........... 1 1.1.1 host interface ................................ ................................ ................................ ................................ ... 1 1.1.2 dsp interface ................................ ................................ ................................ ................................ .... 1 1.1.3 microcontroller interface ................................ ................................ ................................ .................. 1 1.1.4 dram interface ................................ ................................ ................................ ............................... 2 1.1.5 audio playback interface ................................ ................................ ................................ .................. 2 1.1.6 miscellaneous ................................ ................................ ................................ ................................ ... 2 1.2 block diagram ................................ ................................ ................................ .............................. 3 1.3 pin configuration ................................ ................................ ................................ ....................... 4 1.4 pin description ................................ ................................ ................................ .............................. 5 1.5 pin table ................................ ................................ ................................ ................................ ........... 8 1.6 definitions ................................ ................................ ................................ ................................ ..... 11 2. registers description ................................ ................................ ................ 13 3. register table ................................ ................................ ............................... 70 4. characteristics ................................ ................................ ............................ 7 4 5. application notes ................................ ................................ ......................... 75 5.1 dram interface ................................ ................................ ................................ ........................... 75 5.1.1 memory layout ................................ ................................ ................................ ............................... 75 5.1.2 block configuration ................................ ................................ ................................ ........................ 76 5.1.3 linear address v.s. block-offset address ................................ ................................ ....................... 78 5.1.4 16-bit dram ................................ ................................ ................................ ................................ .. 79 5.1.5 edo dram ................................ ................................ ................................ ................................ ... 79
w88113c publication release date: mar. 1999 - ii - revision 0.61 5.2 microcontroller interface ................................ ................................ .............................. 80 5.2.1 direct register addressing ................................ ................................ ................................ ............. 80 5.2.2 general i/o ................................ ................................ ................................ ................................ ..... 81 5.2.3 programmable system clock ................................ ................................ ................................ .......... 81 5.3 host interface ................................ ................................ ................................ ............................ 83 5.3.1 ultra dma mode setting ................................ ................................ ................................ ................ 83 5.3.2 ultra dma data-out ................................ ................................ ................................ ....................... 83 5.3.3 ultra dma error handling ................................ ................................ ................................ ............. 84 5.3.4 ultra dma data-in transfer diagram ................................ ................................ ............................ 84 5.3.5 data-in transfer flowchart example ................................ ................................ .............................. 85 5.3.6 bsy flag control ................................ ................................ ................................ .......................... 86 5.3.7 pin hirq control ................................ ................................ ................................ .......................... 86 5.4 decoder logic ................................ ................................ ................................ ............................. 87 5.4.1 sync detection/insertion ................................ ................................ ................................ ................. 87 5.4.2 descramble ................................ ................................ ................................ ................................ ..... 87 5.4.3 disk-monitor mode ................................ ................................ ................................ ........................ 87 5.4.4 parallel ecc correction ................................ ................................ ................................ ................. 87 5.4.5 edc checking ................................ ................................ ................................ ................................ 88 5.4.6 real time edc checking ................................ ................................ ................................ ............... 88 5.4.7 decoding sequence model ................................ ................................ ................................ .............. 88 5.4.8 disc format selection ................................ ................................ ................................ ..................... 88 5.4.9 cd-da data & q-channel extraction ................................ ................................ ............................. 89 5.4.10 target search ................................ ................................ ................................ ................................ 90 5.4.11 automatic header comparison ................................ ................................ ................................ ..... 90 5.4.12 status collection ................................ ................................ ................................ ........................... 90 5.4.13 decoder processing flow ................................ ................................ ................................ .............. 91 5.4.14 buffer-independent-correction ................................ ................................ ................................ ..... 91 5.4.15 remove frequent srib & automatic cache management ................................ ............................ 92 5.5 audio-playback ................................ ................................ ................................ .......................... 94 5.5.1 configuration phase ................................ ................................ ................................ ........................ 94 5.5.2 playback phase ................................ ................................ ................................ ............................... 94 5.5.3 iec-958 digital audio output ................................ ................................ ................................ ........ 94 5.5.4 audio playback flowchart example ................................ ................................ ................................ 95 6. ordering instruction ................................ ................................ .................. 96 7. how to read the top marking ................................ ................................ .. 96 8. package dimensions ................................ ................................ ..................... 97
w88113c atapi cd-rom decoder & controller publication release date: mar. 1999 - 1 - revision 0.61 1. overview 1. 1 features 1. 1 .1 host interface support atapi cd-rom standard (sff 8020) ultra dma/33 support to achieve high throughput and data integrity 32-byte data fifo to increase data throughput support block-offset transfer and linear address transfer automatic atapi sequence handling automatic data transfer trigger and cache management 1. 1 .2 dsp interface supports cd-rom, cd-rom/xa, cd-i, video-cd, photo-cd, and cd-plus formats supports various types of microprocessors and dsps supports cd-rom data descrambling supports both real-time correction and buffer-independent correction one byte error correction per p-word and q-word supports error detection of cd-rom data automatic repeated error correction real time edc checking logic q-channel extraction by hardware to support precise cd-da data reading using pin bck as subcode reference clock target search and status flag collection to minimize micro-processor overhead 1. 1 .3 microcontroller interface direct register addressing (default) and indirect register addressing support programmable ale pin support 2 programmable general i/o ports and one programmable general input port
w88113c publication release date: mar. 1999 - 2 - revision 0.61 1. 1 .4 dram interface various drams support (128k x 8, 256k x 8, 1m x 8, 64k x 16, 128k x 16, 256k x 16) supports ring-control-register to add flexibility of dram control fpg/edo dram support programmable dram timing programmable refresh timing 1. 1 .5 audio playback interface audio playback in cav mode programmable audio data output pin programmable audio reference clock flexible left-right mute and volume control iec-958 digital audio output 1. 1 .6 miscellaneous flexible power management programmable internal system clock (up to 4 times fast of crystal input) clock output with various frequency 100-pin qfp/lqfp package
w88113c publication release date: mar. 1999 - 3 - revision 0.61 1. 2 block diagram smart dram bandwidth arbitrator 32 bytes data fifo host interface 12 bytes command packet fifo 8/16 bit fpm/edo dram atapi interface subcode interface sync detector & descrambler parallel ecc corrector & edc checker microprocessor interface micro- processor dsp real time edc checker
w88113c publication release date: mar. 1999 - 4 - revision 0.61 1. 3 pin configuration w88113c gnd ra3 cash rd11 rd12/ale1 abck rd14 lrck sdata bck c2po rd15/dj clko/alrck xout xin gnd scsb wfck scsyn exck hrstb/gio1 ud0 ud1 rd13 ud2 ud3 ud4 ud5 ud6 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 gnd rd6 rd7 rd5 rd4 crstb dd7 dd8 sdata1 dd6 dd9 dd5 dd10 dd4 gnd dd11 ale2 dd3 dd12 dd2 arstb/gio2 dd13 asd0 dd1 dd14 dd0 dd15 dmarq hwrb gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 u d 7 u r s / d a 0 d a 2 v d d d a 0 d a 1 a c l k h i r q i o r d y u r d b u w r b u c s b u i n t b d a s p b c s 3 b c s 1 b p d i g a b c s 6 1 b d m a c k b h r d b 3 r d 2 r d c l a s 0 r d 1 r d d v d r a s 7 r a 6 r a 5 r a 4 r a 0 r a 1 r a 2 r a r o e b r w e b r d 9 8 r a 3 r d r d 1 0 / a s d 1 / a s d 2 8 r d
w88113c publication release date: mar. 1999 - 5 - revision 0.61 1. 4 pin description the following convention is used in the pin description table below: (i) denotes an input (o) denotes an output (oz) denotes a tri-state output (od) denotes an open-drain output (i/o) denotes a bi-directional signal miscellaneous pins name no. type pin description rd15/dj 12 i/o ram data 15/drive jumper clko/alrck 13 o clock output/audio lr clock xin xout 15 14 i o crystal input/output - normally, xin and xout are connected to a crystal. hrstb/gio1 17 i host reset - a low active input signal arstb/gio2 60 od atapi reset - a low active output signal. crstb 75 i chip reset - a low-active input signal. vdd 41, 89 power supply pin - 5.0v 5% gnd 1, 16, 30, 51, 66, 80 ground pin micro-controller interface name no. type pin description ud[7:0] 22, 23, 25, 26, 27, 28, 29, 31 i/oz microprocessor data bus - bi-directional processor data lines. urs/gin3/d ao 32 i register select - to select address register or internal register. urdb 33 i microprocessor read strobe - a low-active input signal. uwrb 34 i microprocessor write strobe - a low-active input signal. ucsb 35 i microprocessor chip select - a low-active input signal. rd12/ale1 5 i ram data 12/address latch enable 1 ale2 64 i address latch enable 2 uintb 36 od microprocessor interrupt - a low-active output signal that can be externally wired-or with other interrupt sources.
w88113c publication release date: mar. 1999 - 6 - revision 0.61 audio interface name no. type pin description abck 6 o audio bit clock clko/alrck 13 o audio left/right clock aclk 46 i audio reference clock asd0 58 o audio serial data 0 roeb/asd1 84 o audio serial data 1 rd8/asd2 86 o audio serial data 2 host interface name no. type pin description dd[15:0] 54, 56, 59, 62, 65, 68, 70, 73, 74, 71, 69, 67, 63, 61, 57, 55 i/oz host data bus - signals enable data transfer between the host and w88113a. da[2:0] 40, 44, 42 i host address bus - signals to access various atapi registers. daspb 37 i/od drive active/drive 1 present - a time-multiplexed signal indicating whether a drive is active, or drive 1 is present. cs3b 38 i host chip select 1 - a low-active input signal used to select the host control block registers. cs1b 39 i host chip select 0 - a low-active input signal used to select the host command block registers. pdiagb 43 i/od passed diagnostics - a signal asserted by drive 1 to indicate to drive 0 that diagnostic is completed. cs16b 45 od 16-bit i/o select - a low-active output signal to indicate a 16-bit data transfer. hirq 47 oz host interrupt - a signal to request an interrupt service from host. dmackb 48 i dma acknowledge - a low-active input signal used for dma transfer by the host when dmarq is ready. iordy 49 oz i/o channel ready - when device is not ready for a data transfer request, this signal is negated for extension of the host data transfer cycle within any host register access. hrdb 50 i host i/o read - a low-active read strobe signal. hwrb 52 i host i/o write - a low-active write strobe signal. dmarq 53 oz dma request - a high-active signal asserted for dma data transfer when device is ready to transfer data to or from the host.
w88113c publication release date: mar. 1999 - 7 - revision 0.61 dsp interface name no. type pin description lrck 8 i l/r channel clock - left and right channels are distinguished by this signal. sdata 9 i serial data - serial data from dsp is received from this input. sdata1 72 i serial data - second serial data from dsp is received from this input. bck 10 i bit clock - bit clock from dsp is received from this input. c2po 11 i c2 pointer - c2 error flag from dsp is received from this input. subcode interface name no. type pin description scsd 17 i subcode serial data - subcode serial data from dsp is received from this input. wfck 18 i write frame clock - write frame clock from dsp is received from this input. scsyn 19 i subcode sync - subcode sync from dsp is received from this input. exck 20 i/o external clock - a pin programmed as input or output to supply bit clock for subcode. external ram interface name no. type pin description roeb 84 o external ram output enable - a low-active output signal rweb 88 o external ram write enable - a low-active output signal rd[15:0] 12, 7, 24, 5, 4, 91, 94, 86, 78, 79, 77, 76, 81, 82, 87, 85 i/o ram data bus - data bus for external ram. ra[9:0] 91, 92, 93, 95, 96, 97, 2, 100, 99, 98 o ram address bus - address bus for external ram. cash/l 3, 83 o external ram column address strobe ras 90 o external ram row address strobe
w88113c publication release date: mar. 1999 - 8 - revision 0.61 1. 5 pin table no. name type description remark 1 gnd p ground 2 ra3 o ram address 6ma 3 cash o high byte column address strobe 6ma 4 rd11 i/o ram data 6ma, pu 5 rd12/ale1 i/o ram data/address latch enable 6ma, pu 6 abck o audio bit clock 6ma, pu 7 rd14 i/o ram data 6ma, pu 8 lrck i l/r channel clock 6ma, pu 9 sdata i dsp serial data 10 bck i dsp bit clock 11 c2po i dsp c2 pointer 12 rd15/dj i/o ram data/drive jumper 6ma, pu 13 clko/alrck o clock output/audio lr clock 6ma, pu 14 xout o crystal output 15 xin i crystal input 16 gnd p ground 17 scsb i subcode serial data 18 wfck i write frame clock 19 scsyn i subcode sync 20 exck i/o subcode external clock 6ma, pu 21 hrstb i/od host reset/gio1 6ma, pu 22 ud0 i/o up data 6ma, pu 23 ud1 i/o up data 6ma, pu 24 rd13 i/o ram data 6ma, pu 25 ud2 i/o up data 6ma, pu 26 ud3 i/o up data 6ma, pu 27 ud4 i/o up data 6ma, pu 28 ud5 i/o up data 6ma, pu 29 ud6 i/o up data 6ma, pu 30 gnd p ground
w88113c publication release date: mar. 1999 - 9 - revision 0.61 1.5 pin table, continued no. name type description remark 31 ud7 i/o up data 6ma, pu 32 urs/dao/gin3 i/o up register select/digital audio output 0 general input 3 6ma 33 urdb i up read strobe 34 uwrb i up write strobe 35 ucsb i up chip select 36 uintb od up interrupt 12ma 37 daspb i/od drive active 12ma, pu 38 cs3b i host chip select 1 pu 39 cs1b i host chip select 0 pu 40 da2 i host address pu 41 vdd p power supply 42 da0 i host address pu 43 pdiagb i/od passed diagnostics 12ma, pu 44 da1 i host address pu 45 cs16b od 16-bit i/o select 12ma 46 aclk i audio reference clock 47 hirq o host interrupt 12ma 48 dmackb i dma acknowledge pu 49 iordy o i/o channel ready 12ma 50 hrdb i host read strobe pu 51 gnd p ground 52 hwrb i host write strobe pu 53 dmarq o dma request 12ma 54 dd15 i/o host data 12ma, pu 55 dd0 i/o host data 12ma, pu 56 dd14 i/o host data 12ma, pu 57 dd1 i/o host data 12ma, pu 58 asd0 o audio serial data 0 6ma 59 dd13 i/o host data 12ma, pu 60 arstb i/od atapi reset/gio2 6ma, pu
w88113c publication release date: mar. 1999 - 10 - revision 0.61 1.5 pin table, continued no. name type description remark 61 dd2 i/o host data 12ma, pu 62 dd12 i/o host data 12ma, pu 63 dd3 i/o host data 12ma, pu 64 ale2 i address latch enable 65 dd11 i/o host data 12ma, pu 66 gnd p ground 67 dd4 i/o host data 12ma, pu 68 dd10 i/o host data 12ma, pu 69 dd5 i/o host data 12ma, pu 70 dd9 i/o host data 12ma, pu 71 dd6 i/o host data 12ma, pu 72 sdata1 i dsp serial data 1 73 dd8 i/o host data 12ma, pu 74 dd7 i/o host data 12ma, pu 75 crstb i chip reset pu 76 rd4 i/o ram data 6ma, pu 77 rd5 i/o ram data 6ma, pu 78 rd7 i/o ram data 6ma, pu 79 rd6 i/o ram data 6ma, pu 80 gnd p ground 81 rd3 i/o ram data 6ma, pu 82 rd2 i/o ram data 6ma, pu 83 casl o low byte column address strobe 6ma 84 roeb/asd1 o ram read strobe/audio serial data 1 6ma, pu 85 rd0 i/o ram data 6ma, pu 86 rd8/asd2 i/o ram data/audio serial data 2 6ma, pu 87 rd1 i/o ram data 6ma, pu 88 rweb o ram write strobe 6ma 89 vdd p power supply 90 ras o row address strobe 6ma
w88113c publication release date: mar. 1999 - 11 - revision 0.61 1.5 pin table, continued no. name type description remark 91 rd10/ra9 i/o ram data/ram address 6ma, pu 92 ra8 o ram address 6ma, pu 93 ra7 o ram address 6ma, pu 94 rd9 i/o ram data 6ma, pu 95 ra6 o ram address 6ma 96 ra5 o ram address 6ma 97 ra4 o ram address 6ma 98 ra0 o ram address 6ma 99 ra1 o ram address 6ma 100 ra2 o ram address 6ma 1. 6 definitions asserted/activated: asserted and activated mean that a signal is driven to its true state. block: this term refers to the data in one logical block. the block size depends on the parameter of packet command. block-offset/linear address: the block-offset address is an indirect mapping to the external ram. the offset range is limited by the block size. the linear address is a direct mapping to the external ram. command packet (cp): the command packet is the structure used to communicate commands from a host computer to an atapi device. all cd-rom command packets are 12 bytes in length. data-in/data-out transfer: during the data-in transfer, the data is transferred from device to host. during the data-out transfer, the data is transferred from host to drive.
w88113c publication release date: mar. 1999 - 12 - revision 0.61 decrement/increment: decrement means that a value minus 1. increment means that a value plus 1. negated/de-activated: negated and de-activated mean that a signal is driven to its false state. sector: this term refers to the data contained by one frame time (1/75s for 1x). ultra dma: ultra dma is a data transfer protocol that applies to the ultra dma data burst only. ultra dma burst: an ultra dma burst is defined as the period from an assertion of dmackb to the subsequent negation of dmackb when ultra dma has been enabled by the host. ultra dma crc: cyclical redundancy check is used for the ultra dma protocol to check the validity of the data that has been transferred during last ultra dma burst.
w88113c publication release date: mar. 1999 - 13 - revision 0.61 2. registers description ir - index register (read/write) if dra (5bh.1) is high, the index register is latched at the falling edge of pin ale1 (5) or pin ale2 (64) depending on the setting of ale2 (5ch.3). if dra (5bh.1) is low and pin urs (32) is low, the index register can be accessed by the microprocessor. the value in ir specifies which internal register to be accessed by microprocessor when pin urs (32) is high. note that the 4 least significant bits of ir will increment following each read or write to any register except for pfar (00h,r) . since ir does not automatically increment from 00h to 01h, consecutive reads to address 00h will repeatedly read register pfar (00h,r) . this feature accelerates read operation of atapi command packet. pfar - packet fifo access register - (read 00h) while scod (20h.2) is high, the atapi command packet issued from host is received by the 12-byte packet fifo. flag tendb (01h.r6) is used to check if the packet fifo is full. the microprocessor can read the atapi command packet by repeatedly read register pfar (00h,r) . once the fifo becomes empty, the value ffh will be returned if microprocessor read pfar. the packet fifo can also be used to receive command parameter less than 12 bytes. first, the control bit scod (20h.2) is set high to select the packet fifo to be addressed by the atapi data port. when drq (37h.3) changes from 0 to 1, the lower 4 bits of atblo (34h) is latched as the fifo threshold. upon the number of bytes in the fifo reaches the threshold, flag tendb (01h.r6) becomes active-low and flag fpkt (30h.r1) becomes active-high. once fpkt becomes high, any data writes to the atapi data port is rejected. intctl - interrupt control register - (write 01h) bit 7: pfneen - packet fifo not empty interrupt enable pin uintb (36) is activated when pfneb(01h.r7) becomes active-low if this bit is high. bit 6: tenden - transfer end interrupt enable pin uintb (36) is activated when tendb (01h.r6) becomes active-low if this bit is high. this bit is also automatically enabled if the host issues the packet command (a0h) while hiien (2eh.w7) is high and drive is selected. bit 5: srien - sector ready interrupt enable pin uintb (36) is activated when srib (01h.r5) becomes active-low if this bit is high. this bit is clear to 0 after chip reset, host reset, firmware reset and decoder reset.
w88113c publication release date: mar. 1999 - 14 - revision 0.61 bits 4, 3, 2: reserved bit 1: dten - data transfer enable set this bit high enables the data transfer logic. this bit should be set before trigger any data transfer. in order to reduce the interference of microprocessor, this bit is also automatically enabled during the following operation: trigger adtt (17h.w2) host issues atapi packet command (a0h) while apkten (18h.7) is enabled and drive is selected in case of un-recoverable transfer error, setting this bit low will terminate the current data transfer immediately. bit 0: reserved intrea - interrupt reason register - (read 01h) bit 7: pfneb - packet fifo not empty interrupt flag this bit becomes active-low after packet fifos receive any data issued by the host through atapi data port. pin uintb (36) is activated when this bit becomes active-low if pfneen (01h.w7) is enabled. this flag is deactivated after the last byte is read by microprocessor through register pfar (00h,r) . bit 6: tendb - transfer end interrupt flag this bit beco mes active-low at the end of data transfers. flag tdir (30h.r5) and fpkt (30h.r1) can be used to determine which type of transfer end occurs. pin uintb (36) is activated when this bit becomes active-low if tenden (01h.w6) is enabled. tendb (01h.r6) tdir (30h.r5) fpkt (30h.1) transfer end reason acknowledge register 0 1 0 data-in transfer dhtack (0eh), tack (07h) 0 1 x data-out transfer tack (07h) 0 0 x a0 command packet transfer tack (07h) bit 5: srib - sector ready interrupt flag if rmsri (5ch.0) is low, this bit is used to indicate that one sector is ready to be accessed. if rmsri (5ch.0) is high, this bit is generated only by staerr (80h.r6) , bin0 (80h.r5), dsfuli (80h.r4) , lastbk (80h.r3) , ltti (80h.r2) , tnfi (80h.r1) or hcei (80h.r0) . reading register stat3 (0fh,r) , lsta3 (4bh,r) or tarsta (80h,r) deactivates this flag.
w88113c publication release date: mar. 1999 - 15 - revision 0.61 bit 4: hcib - host command interrupt flag this bit is activated by the following events: host issues atapi soft reset command, if arstien(2fh.1) is enabled host issues command to a non-exist slave drive, if shien(2eh.2) is enabled host issues execute drive diagnostics command, if hiien(2eh.7) is enabled atac(2fh.6) becomes active-high, if hiien(2eh.7) is enabled host set bit srst in atapi device control register, if hiien(2eh.7) is enabled bit 3: tbsyb - transfer busy flag this bit becomes active-low when the data transfer to host is triggered by the following events: writing any value to register thtrg (06h,w) setting bit adtt (17h.w2) high after host read the last byt e to be transferred, this flag is deactivated. bit 2: apib - audio playback interrupt flag if apout (90h,1-0) are not zero, this bit is used as audio-playback-interrupt flag. bit 1: dfrdyb - data fifo ready after data transfer is triggered, the 32-byte data fifos is automatically filled. this bit is used to indicate that the data fifos is ready to be read by the host for debugging. the data fifo is automatically cleared in any of the following conditions: chip reset, host reset and firmware reset dten (01h.w1) is 0 dinb (1fh.w1) is 1 dfrst (2bh.w3) is 1 the end of data-in transfer bit 0: scib - subcode interrupt flag if scien (2ch.w4) is enabled, this bit becomes active-low when one of the following events occurs: iss (22h.r0) becomes active-high nesbk (22h.r1) becomes active-high mss (22h.r2) becomes active-high when subcode interrupt is activated, the microprocessor can read register substa (22h,r) to determine the reason of interrupt. writing register sciack (22h,w) deactivates this flag
w88113c publication release date: mar. 1999 - 16 - revision 0.61 twcl - transfer word counter low- (read/write 02h) before triggering data transfer, the number of words to be transferred should be set through 12-bit transfer word counter (twc). the number of words minus 1 should be written to this counter while using standard atapi 16-bit data transfer. after host read one word, the counter is decreased by one. transfer end interrupt flag , tendb (01h.r6) , is activated when this counter becomes zero. bit 7-0: twch[7:0] - transfer word count low twch - transfer word counter high - (read/write 03h) bit 7: latxf - linear address transfer enable if this bit is high, the linear address transfer is enabled. in this case, the data stored from the address specified by rac (2dh,1dh,1ch) are transferred to host after trigger. the size of transfer data is limited by twc (03h/02h) . setting this bit high cause utby (1fh.r7) high to inhibit up to access ramrd (1eh,r) or ramwr (1eh,w) . if this bit is low, the block-offset transfer is enabled. in this case, the data stored from th e address specified by tbh/l (25h/24h) and tach/l (05h/04h) are transferred to host after trigger. the address of data warps around at the block boundary, so the size of transfer data is limited by block size. bit 3-0: twch[3:0] - transfer word count high tacl/tach - transfer address counter - (write 04h/05h) before triggering block-offset data transfer, the external ram address of data to be transferred should be set through tach/l (05h/04h,w) . this number in this counter specifies the first available data address relative to the beginning of the block. the block number should also be specified through transfer block registers tbh/l (25h/24h) . after one word is read by host, tach/l are incremented to the next available data address. the following equation illustrates the relation between block-offset and linear address: linear address = (block number block size) + address offset thtrg - transfer to host trigger register - (write 06h) this register is used to trigger data transfer regardless of what value is written. if dinb (1fh.1) is low, triggering this register automatically fills the data fifo and then flag dfrdyb (01h.r1) becomes active-low when the data fifo becomes ready. if dinb (1fh.1) is high, data-out transfer is enabled, e.g., parameter of mode-select command. a more convenient way is set adtt (17h.w2) high and then trigger hardware data transfer sequence.
w88113c publication release date: mar. 1999 - 17 - revision 0.61 tack - transfer acknowledge - (write 07h) writing this register deactivates flag tendb (01h.r6) and its corresponding interrupt regardless of what data is written. head0 to head3 - header registers - (read 03h to 07h) these four registers are used to hold the information of header bytes of each sector. header registers should be read soon after stavab (0fh.r7) becomes active-low. note that the header bytes are distrustful if wrong mode is set while ecc is enabled. if bit shden (0bh.w0) is enabled, registers head0-3 are used to hold subheader bytes instead. if control bit qmsf (80h.w4) is set high, the corresponding msf bytes in q-channel information would be automatically loaded into head0-2 (04h-06h,r) when each byte is ready from dsp. notice that the value in register head3 (07h,r) and subh0-3 (14h-17h,r) are not available in this case. bial/biah - buffering initial address - (write 08h/09h) the rule for configuration is that the first byte of the sector is stored at biah/l(09h/08h) - 0ch before enabling the external ram buffering through ctrl0 (0ah,w) , biah/l should be set to control the location of the first byte follows data sync for each data sector. the ram block for buffering is controlled by the number in registers ddbh/l(29h/28h) plus one. for convenience of following data transfer, the microprocessor may set proper value to biah/l after the mode is determined so that the first user data byte will locate at offset 00h of each data block. cd-da yellow book mode 1 & mode 2 cd-rom xa mode 2 biah/l(08h/09h) 000ch fffch fff4h first sync n/a fff0h ffe8h first header n/a fffch fff4h first subheader n/a n/a fff8h first data 0000h 0000h 0000h bacl, bach - buffering address counter - (read 0ah/0bh) after enabling the external ram buffering, buffering write counter is automatically increased by two, beginning from the value specified by biah/l (09h/08h,w) , every time a data word is buffered.
w88113c publication release date: mar. 1999 - 18 - revision 0.61 eial/eiah - ecc initial address - (read 08h/09h, write 0ch/0dh) eiah/l are used to hold the initial address offset of the data block to be corrected. the content of biah/l (09h/08h,w) will be automatically loaded to eiah/l at the beginning of each data sync, making it unnecessary to read or write eiah/l during normal operation. the ram block for ecc is controlled by the number in registers ddbh/l (29h/28h) . ctrl0 - control register 0 - (write 0ah) this register is 0 after chip reset, host reset, firmware reset and decoder reset. bit 7: decen - decoding logic enable setting this bit high enables the decoding logic. bit 6: rtedc - real time edc checking enable setting this bit high enables the real-time-edc-checking logic. the rspc error correction is performed only when the result of real time edc check is error. this function could save about 2/3 of dram bandwidth compared with conventional decoder. bit 5: edcen - error detect and correct enable setting this bit high enables the ecc and edc logic. change of this bit takes effect after next sync. bit 4: acen - automatic correction enable if both m2rq (0bh.w3) and this bit is high, the type of error correction is automatically determined by form bit in the subheader b yte. if only m2rq (0bh.w3) is high, the type of error correction is controlled by f2rq (0bh.w2) . if m2rq (0bh.w3) is low, this bit does not affect the correction of mode 1 data. bit 3: pktinh - obsolete bit 2: bufen - buffering enable setting this bit high enables incoming dsp data buffering. when this bit is high, the values of register head0-3(04h-07h) and subh0-3(14h-17h) are retrieved from external ram rather than from incoming serial data. when bufen is low, any setting of qcen or pcen is mea ningless. change of this bit takes effect after next sync. bit 1: qcen - q-codeword correction enable when this bit is high, q-codeword rspc correction logic is enabled. change of this bit takes effect after next sync. bit 0: pcen - p-codeword correction enable when this bit is high, p-codeword rspc correction logic is enabled. change of this bit takes effect after next sync.
w88113c publication release date: mar. 1999 - 19 - revision 0.61 decen 0ah.7 bufen 0ah.2 edcen 0ah.5 qcen 0ah.1 pcen 0ah.0 decoder mode operation flow 1 1 1 1 1 q-p correction q ? p ? crc 1 1 1 1 0 q-correction q ? crc 1 1 1 0 1 p-correction p ? crc 1 1 1 0 0 buffer-only crc 1 0 0 0 0 disk-monitor no buffering 0 x x x x decoder disable no operation note that if atmsen (9ah.6) is high, the decoder logic will operate in disk-monitor mode before the target is found. when the target is found, the setting of register ctrl1 (0bh,w) will be automatically loaded into decoder logic. ctrl1 - control register 1 - (write 0bh) this register is 0 after chip reset, host reset, firmware reset and decoder reset. bit 7: sien - sync insertion enable when this bit is high, the sector boundary is determined by internal sync insertion logic. bit 6: sden - sync detection enable when this bit is high, the sector boundary is determined by sync bytes of incoming serial data. this bit should not set for reading cd-da data. bit 5: dscren - descrambler enable setting this bit is high enables the descramble logic. this bit should not set for reading cd- da data. bit 4: cwen - corrected data write enable setting this bit high enables corrected data to be written to the external ram. this bit is normally set when correction is enabled by qcen (0ah.w1) or pcen (0ah.w0) . bit 3: m2rq - mode 2 ecc request setting this bit to high enables the cd-rom xa mode 2 correction logic. yellow book mode 1 correction will be performed if this bit is low. bit 2: f2rq - form 2 request setting this bit high request the data to be processed by the cd-rom xa mode-2 form-2 format if m2rq (0bh.3) is high. if m2rq (0bh.3) is high and this bit is low, the cd-rom x1 mode-2 form-1 correction will be performed. this bit is not effective if acen (0ah.w4) is high.
w88113c publication release date: mar. 1999 - 20 - revision 0.61 bit 1: mcrq - mode byte check request when this bit is high, ecc logic will check the 4th header byte with the setting of m2rq (0bh.3) to determine if ecc correction to be performed. bit 0: shden - subheader switch enable when this bit is high, registers head (04h-07h,r) are used to provide subheader bytes. disc format sien (0bh.7) sden (0bh.6) descre n (0bh.5) cwen (0bh.4) m2rq (0bh.3) f2rq (0bh.2) cd-da 1 0 0 0 0 0 yellow book mode 1 1 1 1 1 0 0 yellow book mode 2 1 1 1 0 0 0 cd-rom xa m2f1 1 1 1 1 1 0 cd-rom xa m2f2 1 1 1 x 1 1 stat0 - status register 0 - (read 0ch) bit 7: crcok - cyclic redundancy check ok this bit is used to indicate that the cyclic redundancy check of the latest available sector is passed. bit 6: ilsyn - illegal sync pattern if sden (0bh.w6) is high, this bit becomes high when a sync pattern is detected less than 2352 bytes after last sync pattern was detected/inserted. bit 5: nosyn - no sync pattern if sien (0bh.w7) is high, this bit becomes high when a sync pattern is not detected at 2352 bytes after last sync pattern was detected/inserted. bit 4: lbkf - long block flag if sien (0bh.w7) is low, this bit becomes high when a sync pattern is not detected at 2352 bytes after last sync pattern was detected/inserted. bit 3: wshort - word short this bit becomes high when the incoming serial data rate is too high to be processed. bit 2: sbkf - short block flag if sden (0bh.w6) is low, this bit becomes high when a sync pattern is detected less than 2352 bytes after last sync pattern was detected/inserted.
w88113c publication release date: mar. 1999 - 21 - revision 0.61 status flag sien (0bh.7) sden (0bh.6) internal operation ilsyn(0ch.6) x 1 re-synchronize internal sync logic nosyn(0ch.5) 1 x internal sync logic provide internal sector boundary lbkf(0ch.4) 0 x internal sync logic do not provide internal sector boundary sbkf(0ch.2) x 0 do not re-synchronize internal sync logic bit 1: reserved bit 0: uebk - uncorrectable errors in block this bit is used to indicate that at least one data is corrected in the latest available data block. stat1 - status register 1 - (read 0dh) bit 7-5: bi[2:0] - raw block indicator bi[2:0] block type 000 data block 001 fourth run-in block 010 third run-in block 011 second run-in block 100 first run-in block 101 link block 110 second run-out block 111 first run-out block bit 4: hdera - header erasure this bit is high if there is at least one erasure flag detec ted in header bytes excluding mode byte. erasure in mode byte will cause rmod (0eh.r7-4) all become high. bit 0: shdera - subheader erasure this bit is high if erasure flags are detected for both bytes in at least one subheader byte- pairs. erasures are latched from pin c2po it bufen (0ah.w2) is disabled. otherwise, header and subheader bytes are retrieved from external ram while the following sector is being buffered.
w88113c publication release date: mar. 1999 - 22 - revision 0.61 dhtack - dram to host transfer acknowledge - (write 0eh) writing dhtack, regardless of what data is written, deactivates tendb (01h.r6) that caused by data- in transfer. stat2 - status register 2 - (read 0eh) bit 7-4: rmod[3:0] - raw mode bit rmod2-0 are directly latched from bit 2-0 from the 4th header byte and rmod3 is high if any one of the other 5 bits in the mode byte is high. rmod3 is also high if a mode byte erasure is detected. bit 3: mode2 - mode 2 selected flag this bit reflects the setting of m2rq (0bh.w3) . bit 2: nocor - no correction if ecc logic is enabled by bit edcen (0ah.w5) , and qcen (0ah.w1) or pcen (0ah.w0) , this bit becomes high if ecc logic is interrupted the followings: cwen (0bh.w4) is disabled. mode mismatch is detected while mcrq (0bh.w1) is enabled. mode erasure is detected while mcrq (0bh.w1) is enabled. a mode erasure occurs if the incoming c2po flag is set for the fourth header byte, indicating unreliable mode data. form 2 enabled while ecc logic is set to mode 2. form 2 blocks should not be corrected. form 2 can be enabled by control bit f2rq (0bh.w2), or by the form bit in the subheader byte if acen (0ah.w4) is enabled. form bit erasure while ecc logic is set to mode 2 and acen is enabled. a form bit erasure is detected if the incoming c2po flags are set for both form bits in the subheader bytes. ilsyn (0ch.r6) becomes high while sden (0bh.w6) is enabled bit 1: rfera - raw form erasure this bit becomes high when a form bit erasure was detected. a form bit erasure is detected if the incoming c2po flags are set for both form bits in the submode b ytes (bit 5 in byte 18 and 22). rfera becomes valid when srib (01h.r5) becomes active-low, and remains valid until the next block sync. bit 0: rform - raw form bit this bit is high if the form bit is high in the submode bytes of the incoming serial data. rform becomes valid when flag srib (01h.r5) becomes active-low, and remains valid until the next block sync.
w88113c publication release date: mar. 1999 - 23 - revision 0.61 frst - firmware reset register - (write 0fh) writing this register, regardless of what value is written, trigger a firmware reset. flag frst (2fh.r1) is set by firmware reset. stat3 - status register 3 - (read 0fh) bit 7: stavab - valid status valid this bit is used to indicate that the header, pointer, and status registers about decoder logic are available. this bit should not be used if bicen (9ah.7) is high. bit 5: ecf - error corrected flag this bit is used to indicate that there is at least one byte was corrected in the latest available block. bit 1: c2df - c2 detected in block flag if c2wen (10h.w2) is high, c2df becomes high when there is at least one c2po flag was detected in the previous block. bit 6,4,3,2,0: reserved ctrlw - control-write register - (write 10h) this register is 0 after chip reset, host reset, firmware reset and decoder reset. bit 7: reserved bit 6: swen - synchronized write enable if this bit is high, the change of bufen (0ah.w2) will be synchronized to the end of next sector sync. the buffering of c2po flags is also controlled by this bit if c2wen (10h.w2) and bufen (0ah.w2) are both enabled. this function prevents buffering of an incomplete block. bit 5: sdss - subcode and dsp sync synchronization this bit provides synchronization of cd-da format data. if this bit is high, the writing of incoming serial data to the external ram will start at the first left-channel lower-byte following the end of subcode block. note that this bit should not be used when subcode logic is not enabled. bit 4: dcken - dsp clock enable if this bit is high, clock from dsp is used by internal decoder logic. dcken sho uld be set high before decen (0ah.w7) is set high. bit 3,0: reserved bit 2: c2wen - c2 flag write enable if this bit and bufen (0ah.w2) are both high, the c2 flags of incoming serial data will be latched into the external ram. this operation is synchronized to the end of sync if swen (10h.w6) is high.
w88113c publication release date: mar. 1999 - 24 - revision 0.61 bit 1: drst - decoder reset setting this bit to high resets decoding logic, including: srien (01h.w5) ? 0 ctrl0 (0ah,w) ? 00h ctrl1 (0bh,w) ? 00h ctrlw (10h,w) ? 00h stat0-2 (0ch-0eh,r) ? 00h stat3 (0fh,r) ? 80h tarsta (80h,r) ? 00h drst is automatically cleared by itself. crtrg - correction retry trigger - (write 11h) writing register crtrg, regardless of what data is written, triggers the decoding logic to perform another correction sequence to the same block. bit 7-1: reserved bit 0: crrl - correction retry register load setting this bit high while writing register crtrg (11h,w) re-loads the setting of edcen (0ah.w5) , qcen (0ah.w1) , or pcen (0ah.w0) to decoding logic. decoder parameter updated at the end of sync updated by writing crrl edcen (0ah.w5) yes yes qcen (0ah.w1) yes yes pcen (0ah.w0) yes yes acen (0ah.w4) yes no bufen (0ah.w2) yes no m2rq (0bh.w3) yes no f2rq (0bh.w2) yes no mcrq (0bh.w1) yes no
w88113c publication release date: mar. 1999 - 25 - revision 0.61 mbtc0 - multi-block transfer control 0 - (read/write 12h) the host interface supports multi-block transfer without microprocessor intervention by following sequence: mbc (12h.4-0) ? the number of block to be transferred minus 1 (ex. 3) twch/l (03h/-2h) ? the number of words to be transferred in each block minus 1 (ex. 1175) tach/l (05h/04h) ? the starting point of the block (ex. f4h, ffh) tbh/l (25h/24h) ? the ram block number of the first block to be transferred (ex. 5) atbhi/lo (35h/34h) ? the total bytes to be transferred (ex. 9408) adtt (17h.w4) ? 1 ps: stwcen (18h.3) should not be set in multi-block transfer operation. when adtt is set, host will receive hirq, check status, and then start to read data. after the last word of one block (except the last one) is read by the host, the following hardware sequence is executed: twch/l (03h/02h) ? reload tach/l (05h/04h) ? reload tbh/l (25h/24h) ? auto-increment mbc0 (12h.4-0) ? auto-decrement flag tendb (01h.r6) only becomes active at the end of data transfer of the last block. this register is 0 after chip reset, host reset and firmware reset. 3 2 1 0 n n+1 n+2 n+3 5 6 7 8 mbc(12h.4-0) tbh/l(25h/24) data transfer tendb(01h.r6) hirq transfer trigger status complete twc/tac reload twc/tac reload twc/tac reload
w88113c publication release date: mar. 1999 - 26 - revision 0.61 bit 7: mbvab - multi-block counter valid flag this bit is used to indicate that mbc (12h.4-0) is stable enough to be monitored by microprocessor. there is no need to monitor this bit in normal operation. bit 6: mbinc - multi-block increment flag this bit becomes active-high if microprocessor sets incmbc (13h.w0) and multi-block number increment has not completed. there is no need to monitor this bit in normal operation. bit 4-0: mbc[4:0] - multi-block counter before triggering multi-block transfer, the number of blocks to be transferred minus 1 should be written to mbc (12h.4-0) . single block transfer is performed if mbc (12h.4-0) is zero. there is no need to mo nitor this counter normal operation. mbtc1 - multi-block transfer control 1 - (read/write 13h) this register is for debug only. this register is 0 after chip reset, host reset and firmware reset. bit 7-3: reserved bit 2: mbtien - multi-block transfer interrupt enable if mbtien and mbtfen are both enabled, pin uintb (36) will activate at the end of data transfer of each block if the block count in mbc (12h.4-0) is not zero. there is no need to set this bit in normal operation. bit 1: mbtfen - multi-bl ock transfer interrupt flag enable if this bit is high, mbti (30h.r4) will be activated at the end of data transfer of each block if the block count in mbc (12h.4-0) is not zero. there is no need to set this bit in normal operation. bit 0: incmbc - increment multi-block counter setting this bit high increments mbc (12h.4-0) . this function is useful in data transfer to host by dma mode. because data byte count is not specified in dma mode transfer, the number of block to be transferred can be incre mented when a new block becomes available before the transfer is completed. ectrl - enhanced control register - (write 14h) bit 7-2: reserved bit 1: ir7f - provide flag utby at ir7 when this bit is high, flag utby (1fh.r7) can be monitored by read bit-7 of the index register.
w88113c publication release date: mar. 1999 - 27 - revision 0.61 bit 0: disai - disable auto-increment of microprocessor-ram address counter when this bit is high, the automatic increment of the rac (2dh/1dh/1ch) address counter is disabled. note that disai should be 0 before rftrg (2ah.w6) is triggered. subh0 to subh3 - subheader registers - (read 14h to 17h) these registers are used to hold the information of subheader bytes. if bufen (0ah.w2) is disabled, subheader bytes are latched from incoming serial data. if bufen (0ah.w2) is enabled, subheader bytes are retrieved from the external ram. astrg - automatic sequence trigger register (write 17h) the following bits will clear themselves after the triggered operation are completed. bit 7: reserved bit 6: csrt - clear soft reset trigger setting this bit high clears bit srst in the atapi device control register. bit 5: dsct - disk seek complete trigger if abyen (18h.1) is high, setting dsct high triggers the following operations: set bsy dsc (37h.4) ? 1 clear bsy if abyen (18h.1) is low, setting dsct high sets dsc(37h.4) to 1. bit 4: sigt - atapi signature trigger setting this bit high initialize the task registers with atapi signature. atfea (31h) ? 00h aterr (31h) ? 01h atint (32h) ? 01h atspa (33h) ? 01h atblo (34h) ? 14h atbhi (35h) ? ebh atsta (37h) ? x00x0000b note that register atdrs (36h) is not cleared by triggering sigt to abide by the atapi protocol.
w88113c publication release date: mar. 1999 - 28 - revision 0.61 bit 3: cpft - clear packet fifo trigger setting this bit high clears the packet fifo. bit 2: adtt - automatic data transfer trigger if pio (1fh.2) is high, setting adtt high triggers the following pio data transfer sequence: set bsy dten (01h.w2) ? 1 scod (20h.2) ? 0 if dinb (1fh.1) is 0; otherwise, 1 atint (32h) ? 02h if dinb (1fh.1) is 0; otherwise, 00h if stwcen (18h.w3) is enabled, then atbhi/lo ? (twch/l + 1) 2 the data transfer logic will start to fill the data fifo automatically. the following sequence will be executed when dfrdyb (01h.r1) become active-low: drq (37h.3) ? 1 clear bsy hirq (2eh.3) ? 1 after detecting the interrupt, the host will check the status and then read the data. stwcen (18h.3) should not be used for automatic multiple block transfer. instead, atblo, atbhi should be set by firmware to: (mbc + 1) ((twc + 1) 2) if pio (1fh.2) is low, setting adrtg high triggers the following dma data read sequence: set bsy dten (01h.w1) ? 1 scod (20h.2) ? 0 if dinb (1fh.1) is 0; otherwise, 1 atint (32h) ? 02h if dinb (1fh.1) is 0; otherwise, 00h bit 1: drqt - drq trigger if bit pio (1fh.2) is high, setting this bit high triggers the following hardware sequence: drq (37h.3) ? 1 bsy ? 0 hirq (2eh.3) ? 1 when bit pio is low (dma mode), this bit should not be triggered. bit 0: sct - status completion trigger setting thi s bit high triggers the following hardware sequence: check (37h.0) ? acheck (3eh.0) corr (37h.2) ? acorr (3eh.2) drdy (37h.6) ? adrdy (3eh.6) atint (32h) ? 03h
w88113c publication release date: mar. 1999 - 29 - revision 0.61 clear bsy hirq (2eh.3) ? 1 apkten (18h.7) ? 1, if autoen (18h.4) is high ascen (18h.5) ? 0 after detecting the interrupt, the host reads the atapi status register and if necessary, the error register for the command completion status. asctrl - automatic sequence control register - (read/write 18h) bit 7: apkten - automatic packet t ransfer enable setting this bit high enables automatic packet transfer logic. when apkten is high, the following hardware sequence is performed if host issues opcode a0h to the ata command register if drive has been selected: set bsy (37h.7) apkt (30h.r0) ? 1 clear packet fifo aterr (31h) ? 00h atint (32h) ? 01h dten (01h.w1) ? 1 tenden (01h.w6) ? 1, if hiien (2eh.7) is high scod (20h.2) ? 1 check (37h.0) ? 0 corr (37h.2) ? 0 drq (37h.3) ? 1 dsc (37h.4) ? 1, if asdsc (3dh.4) is high drdy (37h.6) ? 1 hirq (2eh,3) ? 1, if a0ien (18h.0) is high apkten ? 0 clear bsy (37h.7) atac (2fh.w6) will not be activated during automatic packet transfers. when the drive becomes ready after bsy is cleared, the host starts to issue 12-byte atapi command packet. reception of the 6th packet word activates the following events. fpkt (30h.r1) ? 1 tendb (01h.r6) ? 0 pin uintb activate if tenden (01h.w6) has been enabled
w88113c publication release date: mar. 1999 - 30 - revision 0.61 writing any value to register tack (07h) deactivates apkt, tendb, and corresponding interrupt. bit 6: adcen - automatic drq clearing enable when this bit is high, drq (37h.3) is cleared to 0 and bsy (37h.7) is set to 1 after the end of following transfers: host reads from external ram host writes to command packet fifo bit 5: ascen - automatic status completion enable when this bit is high, status completion is performed after the end of the following transfers: host reads from external ram host writes to command packet fifo adcen (18h.6) should be enabled when ascen is enabled to provide clearing of drq (37h.3) and setting of bsy (37h.7). if both adcen and ascen are enabled, the following hardware sequence is executed at the end of one of the above data transfers: set bsy drq (37h.3) ? 0 check (37h.0) ? acheck (3eh.0) corr (37h.2) ? acorr (3eh.2) drdy (37h.6) ? adrdy (3eh.6) atint (32h) ? 03h clear bsy hirq (2eh.3) ? 1 apkten (18h.7) ? 1, if autoen (18h.4) is high ascen (18h.5) ? 0 after detecting the interrupt, the host reads the atapi status register and if necessary, the error register for the command completion status. bit 4: autoen - automatic apkten set after status completion enable when this bit is high, apkten (18h.7) will be set after automatic status completion sequence triggered by either sct (17h.0) or ascen (18h.5). bit 3: stwcen - set transfer word count enable when this bit is high, the value (twch/l + 1) 2 is loaded into atblo and atbhi when adtt (17h.2) is triggered and pio (1fh.2) has been set high. if acmen (9ch.6) is not enabled, control bit stwcen should not be set for multiple block transfer. instead, atbhi/lo should be set by firmware to: (mbc4-0 + 1) (twch/l + 1) x 2 .
w88113c publication release date: mar. 1999 - 31 - revision 0.61 bit 2: aucrcen - automatic ultra dma crc error logic enable if aucrcen (18h.2) is set high, the automatic status complete logic would be stopped if ucrcokb (30h.r3) is high. if no crc error has occurred in last ultra dma burst, status complete sequence would be automatically executed. this bit should be set high only if ascen (18h.5) is set high as well. this bit is automatically clear when: (1) automatic status complete sequence is triggered or (2) sct (17h.w0) is set high. bit 1: abyen - automatic bsy set enable when this bit is high, the following sequence is executed when disk seek complete is triggered by dsct (17h.w5) : set bsy dsc (37h.4) ? 1 clear bsy dsct ? 0 bit 0: a0ien - a0h command interrupt enable if this bit is high and apkten (18h.7) has been enabled, hirq (2eh.3) becomes active-high after an opcode a0h is issued to ata command register. cctl0 - clock control register 0 - (write 19h) this register is 0 after chip reset. bit 7: ckstp - clock stop setting his bit high stops the internal clock and the clock output at pin clko. ckstp is de- activated by the following events: chip reset or host reset or firmware reset command write from the host while the drive is selected host issues diagnostic command, regardless of drive selection host issues command to shadow drive if shdrv (3fh.6) is enabled host set bit srst in atapi device control register high, regardless of drive selection bit 6: reserved bit 5: jpss - jumper sampling select this bit is used to control the sampling of pin rd15/dj. when jpss is high, pin rd15/dj is sampled while chip reset is active. when this bit is low, par/jp is sampled while chip reset or host reset are active. bit 4: reserved bit 3-0: cks[3:0] - clock skew control cks3-0 are used to control the duty cycle of the internal clock. the low period of cycle increases as the skew value increments.
w88113c publication release date: mar. 1999 - 32 - revision 0.61 cctl1 - clock control register 1 - (write 1ah) this register is 0 after chip reset. bit 7: clkoen setting this bit high enable pin clko (13) as clock output if apout (90h.1-0) is zero. clkoen (1ah.7) apout1-0 (90h.1-0) function of pin 13 remark 0 0 tri-state with internal pull-up default 1 0 clock output x not 0 audio lrck output bit 6: tsync - test synchronization control when this bit is high, the detected/inserted sync can be monitored from pin clko (13). bit 5: xininv - inverted xin as system clock when this bit is high, the intern al system clock is inverted from crystal input pin xin (15). bit 4: psken - programmable system clock enable when this bit is high, the frequency of internal system clock is controlled by register pskctl (59h). bit 3,2: clk[1:0] - pin clko select clk1-0 frequency of clko remark 0 sf ? 2 default 1 sf ? 4 2 sf ? 1 3 reserved sf is the system frequency. notice that the relation between system frequency and crystal frequency depends on the setting of xtald2 (1ah.w0) and psken (1ah.w4). bit 1: reserved bit 0: xtald2 - crystal divided by 2 the internal clock frequency is half of crystal frequency if this bit is high. ver - version register - (read 1ah) this register is used to hold the version number.
w88113c publication release date: mar. 1999 - 33 - revision 0.61 dspsl - dsp selection register - (write 1bh) bit 7: c2ml - c2 msb to lsb when this bit is high, the sequence of erasures via pin c2po (11) is from msb to lsb. bit 6: s16o - select 16 offset the incoming serial data is latched one clock after pin lrck (13) changes if this bit is high. bit 5: lchp - left channel polarity the incoming serial data is latched as left channel when pin lrck (13) is high if this bit is high. bit 4: sft8 - shift 8 clocks the incoming serial data is latched by delay 8 clocks if this bit is high. bit 3: reserved bit 2: sel16 - select 16 bits per channel the incoming serial data is latched 16 times per channel if this bit is high. bit 1: dir - data direction setting this bit high selects the direction of data from pin sdata (9) from msb to lsb. bit 0: edge - latching edge s elect setting this bit high selects the rising edge of bck for latching data from pin sdata (9) . dsp setting example: dspsl dsp data format 07h toshiba 24h sanyo a3h sony 48-bit slot c3h philip c2beb - c2 block error byte - (read 1bh) the block error byte is the or of all the c2 error flag bytes. racl, rach, and racu - ram address counter - (write 1ch, 1dh, 2dh) these three registers are used to set linear address of the external ram. before accessing registers ramrd/ramwr or triggering linear-address transfer, microprocessor should set these registers. the microprocessor should write the ram starting address into the counter while busy flag utby (1fh.r7) is low. then this counter increases automatically each time when a byte is read or written.
w88113c publication release date: mar. 1999 - 34 - revision 0.61 ramwr - ram write register - (write 1eh) to gain access to external ram, the microprocessor should first wait for flag utby (1fh.r7) to become low, then set the address through raclu/h/l(2df/1dh/1ch) . writing data into register ramwr triggers the following sequence: data is transferred from the microprocessor to register ramwr. data is transferred from ramwr to the ram located by the address counter. increments racl, rach, and racu increments by one clear flag utby ramrd - ram read register - (read 1eh) to gain access to external ram, the microprocessor should first wait for flag utby (1fh.r7) to become low, then set the address through raclu/h/l (2df/1dh/1ch) . writing data into register ramrd triggers the following sequence: data previously stored in ramrd is transferred to the microprocessor. ram data located by the address counter is transferred to the ramrd register. increments racl, rach, and racu increments by one clear flag utby note that the first data read from ramrd is invalid. hictl0 - host interface control register - (write 1fh) bit 7-6: reserved bit 5: h16s - (obsolete) no matter what value is set, the data transfer between host and decoder is using 16-bit protocol. bit 4: laen - latch enable if this bit is high, host address and chip-select signals will be latched when pins hrdb or hwrb change from high to low. bit 3: mdma - multi-word dma mode setting this bit to high enables multi-word dma mode if pio (1fh.2) is low. bit 2: pio - pio/dma mode select setting this bit high causes data transfer to/from host using pio mode. this bit is also controlled by bit-0 of atfea (1f1h/171h) if asmda (5bh.7) is high. bit 1: dinb - data-in transfer enable setting this bit low select data-in transfer. otherwise, the data-out transfer i s enabled.
w88113c publication release date: mar. 1999 - 35 - revision 0.61 bit 0: udma - ultra dma enable setting this bit high selects data transfer protocol as ultra dma. the bandwidth of ultra dma depends on the system frequency and the setting of udt1-0 (8ah.5-4) . hictl0 (1fh,w) data-in data-out pio mode xch xeh mdma mode x8h xah udma mode x9h xbh stat5 - status register 5 - (read 1fh) bit 7: utby - microprocessor to ram transfer busy when the microprocessor-to-ram transfer is not complete, this bit is high. bit 6-4: reserved bit 3: mdma - multi-word dma mode bit 2: pio - pio/dma mode select bit 1: dinb - data-in transfer enable bit 0: udma - ultra dma enable hictl1 - host interface control register - (write/read 20h) the value in this register is 26h after chip reset. bit 7 : reserved bit 6: pdiagen - pin pdiagb enable setting this bit high causes pin pdiagb to the active-low state. pdiagen is automatically de-activated, causing pin pdiagb to be high-impedance, by the following events: reception of execute drive diagnostics command (ata opcode 90h) reception of ata soft reset (srst) chip reset or host reset bit 5: daspen - pin daspb enable setting this bit high activates pin daspb. daspen is automatically de-activated, causing pin daspb to be high-impedance, by the following events: reception of execute drive diagnostics command (ata opcode 90h) reception of ata soft reset (srst)
w88113c publication release date: mar. 1999 - 36 - revision 0.61 chip reset or host reset this bit is also controlled by dasps2 (3fh.2), dasps1 (3fh.1) and daspss (3fh.0). bit 4: clrbsy - clear bsy setting this bit high causes the fl ag bsy in the atapi status register to become low if apkt (30h.r0) is not high. this bit is self-clear after the bsy is clear. bit 3: setbsy - set bsy setting this bit high causes the flag bsy in the atapi status register to become high if apkt (30h.r0) is not high. this bit is self-clear after the bsy is set. bit 2: scod - select command-packet-fifo or data the data received from atapi data port is stored in packet fifo if this bit is high. this bit is also controlled by adtt (17h.w2) and apkten (18h.7) . bit 1: rdyen - pin iordy enable setting this bit high enables iordy (pin 49) to work with hrdb (pin 50). bit 0: io16en - pin iocs16b enable setting this bit high allows pin iocs16b to become active-low when 16-bit data access is in use. this bit should be enabled in normal operation. sictl0 - subcode interface control register 0- (write 21h) bit 7-4: reserved bit 3: pqenb - p-data or q-data enable bits 7 and 6 of subcode data are written to the external ram if this bit is low. bit 2-0: subcs[2:0] - subcode clock select these bits are used to select subcode clock rate. subcs[2:0] disk speed subcode block rate 0 1 fold 75 sectors/sec 1 2 fold 150 sectors/sec 2 4 fold 300 sectors/sec 3 - reserved 4 6 fold 450 sectors/sec 5 8 fold 600 sectors/sec 6 - reserved 7 - reserved
w88113c publication release date: mar. 1999 - 37 - revision 0.61 sciack - subcode interrupt acknowledge - (write 22h) writing any value to this register de-activates scib (01h.r0) if scien (2ch.w4) is enabled. substa - subcode status register - (read 22h) when scib (01h.r0) is activated, the microprocessor can read this register to determine the reason of interrupt. bits 7-5: reserved bit 4: qcrcok - q-channel crc ok flag if q-channel extraction is enabled, this bit reflects the status of crc checking of q-channel information. bit 3: reserved bit 2: mss - missing subcode sync a missing-subcode-sync sets mss high and negates scib (01h.r0). a microprocessor interrupt is activated also if scien (2ch.w4) is enabled. bit 1: nesbk - normal end of subcode block a normal-subcode-block-en d sets nesbk high and negates scib (01h.r0) . a microprocessor interrupt is activated also if scien (2ch.w4) is enabled. bit 0: iss - illegal subcode sync an illegal-subcode-sync sets iss high and negates scib (01h.r0) . a microprocessor interrupt is activated also if scien (2ch.w4) is enabled. tbh/l - transfer block register - (read/write 25h/24h) if latxf (03h.7) is low, tbh/l form a 9-bit counter that is used to specify the first ram block to be transferred, while registers tach/l (05h/04h,w) specify the starting address relative to the beginning of this ram block. the block-offset transfer is carried within a transfer ring that is controlled by dtrch/l (53h/52h) and dtrbh/l (51h/50h) . the buffer ring and transfer ring are usually defined in the same range. note that tbh/l (25h/24h) do not increment automatically at the end of each transfer unless: acmen (9ch.6) is high dinb (1fh.1) is low (data-in transfer is enabled) latxf (03h.7) is low (block-offset transfer is used) if acmen (9ch.6) is high, tcc (9dh) minus n and tbh/l (25h/24h) plus n right after skipc (9eh) is set n . if bicen (9ah.7) is high and bcfsel (9ah.5) is low, the dsp buffering stop when buffering block (internal) reach tbk (9bh,w) .
w88113c publication release date: mar. 1999 - 38 - revision 0.61 scbh/l - subcode block register - (read/write 27h/26h) scbh/l (27h/26h) form a 9-bit counter that contains the block number of the latest available subcode data that can be read by the host. the number in scbh/l (27h/26h) plus 1 points to the ram block that is buffering incoming subcode. the number in scbh/l (27h/26h) increments at the end of subcode block buffering. if sdbs (88h.4) is high, the buffering of subcode is controlled by ddbh/l (29h/28h) rather than scbh/l (27h/26h) . ddbh/l - decoded data block register - (read/write 29h/28h) ddbh/l(29h/28h) form a 9-bit counter that contains the number of the latest available decoded data block after decoder interrupt occurs. cd-rom sector data buffering is a block-based ring operation. in real-time-correction (rtc) mode, i.e., bicen (9ah.7) is low, if the number in ddbh/l (29h/28h) is n - 1 , then the current sector is buffered into block with number n . the ddbh/l (29h/28h) increments at each sync. when the decoded-block-number equals the value in wbrch/l (57h/56h) , the sector is buffered into the block with number specified by wbrbh/l (55h/54h) . in buffer-independent-correction (bic) mode, i.e., bicen (9ah.7) is low, ddbh/l (29h/28h) increments at the end of edc-checking if there is no staerr (80h.r6) or hcei (80h.r0) error. ramcf - ram configuration register - (read/write 2ah) this register is 0 after chip reset. bit 7: rftyp - refresh type the refresh mode of dram is cas-before-ras if this bit is high. the refresh mode of dram is ras-only if this bit is low. bit 6: rftrg - ram filling trigger setting this bit high triggers the dram filling. all locations in the external ram will be filled with the value in register ramwr (1eh,w) . the value (ex:00h) should be written to registers racl, racu, and rach before triggering rftrg. flag rfc (2ah.r5) will change from 0 to 1 when all ram locations have been filled. after ram filling has completed, the microprocessor should clear rftrg to 0. bit 5: rfc - ram fill completion flag (read only) this flag will change from 0 to 1 when all ram locations have been filled with the value in register ramwr (1eh,w) . this flag is clear when rftrg is disabled.
w88113c publication release date: mar. 1999 - 39 - revision 0.61 bit 5: reserved (write only) bit 4: swap - host high-low swap setting this bit high causes the host access of high/low byte to be swapped. bit 3: reserved bit 2-0: rtc[2:0] - external ram type configuration bits the external ram should be appropriately configured by these three bits according to its specification. rtc[2:0] are de-activated by chip reset or host reset, but are not changed by firmware reset. rtc[2:0] ram configuration 0,1, 4, 7 reserved 2 256k x 4-bit x 2, 256k x 8-bit x 1, 128k x 8-bit x 1, 8-row 9-column 3 128k x 8-bit x 1, 9-row 8-column 4 64k x 16-bit x 1, (8-row 8-column) 128k x 16-bit x 1 (9-row 8-column) 128k x 8-bit x 2 (9-row 8-column) 5 256k x 16-bit x 1 128k x 16-bit x 1 (8-row 9-column) 128k x 8-bit x 2, (8-row 9-column) 6 1 m x 4-bit x 2 note: the control bit ale2 (5ch.3) must be set while using 16-bit dram. memcf - memory layout configuration register - (write 2bh) bits 7-6: reserved bits 5-4: dbaf[1:0] - dram bus arbitration factor the value in control bits dbaf1-0 (2bh.w5-4) defines the dram bus arbitration factor, daf , which can adjust the number of cycles between two host transfer pre-fetch cycles is at most 2 da f . if less bandwidth is demanded by logic other than host transfer, the bandwidth is automatically arbitrated to achieve the best performance. if the value in these bits is 0 after chip reset and firmware reset. bit 3: dfrst - data fifo reset setting this bit high resets data fifo. this bit is not self-clear. bit 2: frdy - fast pin iordy enable setting this bit high accelerates the de-assertion of pin iordy (49) without referring pin hrdb (50) .
w88113c publication release date: mar. 1999 - 40 - revision 0.61 bit 1-0: rlc[1:0] - external ram layout configuration bits the memory layout configuration should be set as shown in the following table: rlc[1:0] block size 0,1 -- 2 c00h 3 a00h the block size should be set as c00h if c2wen (10h.w2) is enabled. sictl1 - subcode interface control register 1 - (write 2ch) bit 7: sbxck - subcode external clock the external clock from pin exck (20) is used by the subcode logic if this bit is high. bit 6: scen - subcode enable setting this bit high enables the subcode logic. bit 5: cd2sc - clock divided by 2 for subcod e logic the subcode clock is divided by two if this bit is high. bit 4: scien - subcode interrupt enable setting this bit high enables subcode interrupts. bit 3: exinv - external clock invert select if exop (2ch.w2) is high, setting this bit high selects an inverted clock output at pin exck (20) . bit 2: exop - pin exck operation setting this bit high sets pin exck (20) as an output. bit 1-0: scf[1:0] - subcode format select scf[1:0] subcode format 0 smd0 (philips) 1 smd1 (eiaj-1) 2 smd2 (eiaj-2) 3 reserved
w88113c publication release date: mar. 1999 - 41 - revision 0.61 misc0 - miscellaneous control register 0 - (write 2eh) bit 7: hiien - host interface interrupt enable setting this bit high enables the microprocessor interrupt of the host interface. host interface interrupt occurs at the following conditions: srst (device control register) is written as 1 after 0 to either master or slave drive. execute drive diagnostics command is written to either master or slave drive. any opcode is written to the atapi command register while the drive is selected except: (1) command opcode is 08h, (2) command opcode is a0h and apkten (18h.7) is high. ide interface interrupt is cleared by the following: chip reset or host reset reading register 37h writing 1 to clrbsy (20h.4) bit 6: reserved bit 5: drveb - drive selection enable setting this bit low enables selection of the drive if bit drv in atapi drive select register matches the setting of mdrv (2eh.4) . bit 4: mdrv - master drive setting this bit high sets the drive to be selected when bit drv in the atapi drive s elect register is set to 0 (master drive). bit 3 : hirq - host interrupt request set this bit high asserts interrupt at pin hirq if the drive is selected and nien is enabled in the atapi device control register. hirq is also automatically set by the following: automatic packet transfer sequence, enabled by apkten (18h.7) automatic status completion sequence, enabled by sct (17h.w0) or ascen (18h.5) hirq is automatically de-activated by the following: chip reset or host reset set bit srst in the atapi device control register high host issue ata command while the drive is selected host read atapi status register while the drive is selected bit 2: shien - shadow command interrupt enable setting this bit high enables the microprocessor interrupt for the shadow command. pin uintb (36) becomes low-active when shdc (2fh.r5) becomes high-active if this bit is enabled. bit 1, 0: reserved
w88113c publication release date: mar. 1999 - 42 - revision 0.61 miss0 - miscellaneous status register 0 - (read 2eh) bit 5: srub - status register updated flag this bit becomes high w hen the atapi status register is updated by the following: microprocessor writes to 37h microprocessor triggers dsct (17h.w5) microprocessor triggers sct (17h.w0) automatic status completion occurs if ascen (18h.5) is enabled reception of a0h command if apkten (18h.7) is enabled chip reset or host reset bit 4: mdrvf - master drive flag this bit is high if the drive is configured as master. this bit is low if the drive is configured as slave. bit 3: hintf - host interrupt flag this bit reflects the statu s of the source of pin hirq (47) . bit 2: nien - bit nien in device control register this bit reflects the value of bit nien in atapi device control register. bit 1: pdiagb - pin pdiagb flag this bit reflects the status of pin pdiagb (43). bit 0: daspb - pin daspb flag this bit reflects the status of pin daspb (37). misc1 - miscellaneous control register 1 - (write 2fh) this register is 0 after chip reset. bit 7: arrc - atapi register read control when this bit is high, the atapi registers can be read regardless of the value of bsy if the drive is selected. bit 6: sarrc - shadow drive atapi register read control when this bit is high, the shadow atapi registers can be read regardless of the value of bsy if the shadow drive is selected.
w88113c publication release date: mar. 1999 - 43 - revision 0.61 bit 5-4: hrsts[1:0] - hrstb pin function select hsts[1] hsts[0] type function of pin 21 remark 0 0 i/od gio1 default 0 1 o da1 1 0 i hrstb 1 1 i hrstb bit 3-2: arsts[1:0] - arstb pin function select arsts[1] arsts[0] type function of pin 60 remark 0 0 i/od gio2 default 0 1 o da2 1 0 od arstb (reset-mode) 1 1 od arstb (interrupt-mode) when arsts1 is high, pin arstb (60) becomes active-low if host writes an atapi soft reset command. in interrupt-mode, writing any value to register arstack (30h,w) de- activates pin arstb (60) . in reset-mode, pin arstb (60) automatically de-activates itself after 256 system clock. bit 1: arstien - atapi soft reset interrupt enable when this bit is high, pin uintb (36) becomes active-low whenever host writes an atapi soft reset command (opcode is 08h). bit 0: arwc - atapi register write control host writes to atapi registers (except device control register) will not take effect when arwc and bsy are high, if bsy is not set by the following commands: opcode 90h is written to ata command register while the drive is selected. opcode 90h is written to ata command register while the shadow drive is selected if shdrv (3fh.6) if high. miss1 - miscellaneous status register 0 - (read 2fh) bit 7: srst - soft reset flag this bi t becomes high when host writes 1 to bit srst in the atapi device control register if either master or slave drive is selected. when srst becomes high, the following events will be executed: bsy (37h.7) ? 1 initialize atapi signature pdiagen (20h.w6) ? 0 and disables pin pdiagb (43) to high-impedance state
w88113c publication release date: mar. 1999 - 44 - revision 0.61 disable pin daspb (37) to high-impedance state if daspss (3fh.0) is low. negates pin daspb (37) if daspss (3fh.0) is high. ckstp (19h.7) ? 0 activates host interrupt to the microprocessor if hiien (2eh.w7) is high. hirq (2eh.w3) ? 0 host interrupt is cleared by read register atcmd (37h) or write clrbsy (20h.4) . srst is de-activated by read register miss1 (2fh,r) after srst is set to low by host. bit 6: atac - atapi command if the drive is selected, this bit becomes high when any command is written to the atapi command register except the following opcode are received. opcode is 90h opcode is 08h and either arst1 (2fh.w3) or arstien (2fh.w1) is enabled opcode is a0h and apkten (18h.w7) is high atac is de-activated by the following: chip reset or host reset reading register atcmd (37h) writing 1 to clrbsy (20h.4) bit 5: diag - execute drive diagnostics command this bit becomes high if execute drive diagnostics command (opcode 90h) has been written to either master or slave drive. meanwhile, the following events will be executed: bsy(37h.7) ? 1 pdiagen (20h.w6) ? 0 and disables pin pdiagb to high-impedance state ckstp (19h.7) ? 0 atapi error register ? 01h atapi feature register ? 00h atapi interrupt reason register ? 01h atapi sam tag byte ? 01h atapi byte counter register low/high ? 00h atapi drive select register ? 00h clear atapi status register except bit bsy and service activates host interrupt to the microprocessor if hiien (2eh.w7) is enabled
w88113c publication release date: mar. 1999 - 45 - revision 0.61 bit 4: shdc - shadow command flag this bit becomes high when the host writes a command to a non-existent slave drive. meanwhile, pin uintb (36) becomes low-active if shien (2eh.w2) is enabled. atac is de- activated by the following: chip reset or host reset reading register atcmd (37h) writing 1 to clrbsy (20h.4) bit 3: arst - atapi soft reset flag this bit becomes high when atapi soft reset command (opcode 08h) is written to either master or slave drive. arst is de-activated by writing any value to register arstack (30h,w). bit 2: rst - reset flag this bit is high when the chip is currently being reset by chip reset, host reset, or firmware reset. bit 1: frst - firmware reset flag this bit is high if the current or most recent reset was f irmware reset. the first read of register miss1 (2fh,r) following the end of the firmware reset clears this flag to 0. bit 0: hrst - chip reset or host reset flag this bit is high if the current or most recent reset was activated by chip reset or host reset. the bsy flag is set whenever chip reset or host reset is activated. the first read of register miss1 (2fh,r) following the end of the chip reset or host reset clears this flag to 0. arstack - atapi soft reset acknowledge (write 30h) writing any value to this register triggers the following events: clears arst (2fh.r3) deactivates pin arstb if arsts1-0 (2fh.w3-2) is 3 deactivates pin uintb if arstien (2fh.w1) is enabled miss2 - miscellaneous status register 0 (read 30h) bit 7: srstd - soft reset with drq this bit becomes high if host activates srst in the atapi device control register while drq is high and the drive is selected. this bit is updated at rising edge of srst.
w88113c publication release date: mar. 1999 - 46 - revision 0.61 bit 6: cmdc - command conflict this bit becomes high if one of the fo llowing events occurs while bsy is high: host writes any opcode to atapi command register while drive is selected. host writes any opcode to atapi command register while shadow drive is selected and shdrv (3fh.6) is enabled. host writes opcode 90h (execute drive diagnostics) to atapi command register. cmdc is updated each time the host writes the atapi command register. bit 5: tdir - data transfer direction tendb (01h.r6) tdir (30h.r5) fpkt (30h.1) transfer end reason acknowledge register 0 1 0 data-in transfer dhtack (0eh) 0 1 x data-out transfer tack (07h) 0 0 x a0 command packet transfer tack (07h) bit 4: mbti - multi-block transfer interrupt this flag indicates the end of each block transfer while the multi-block transfer is used. bit 3: ucrcokb - ultra dma crcok/ram parity interrupt flag this bit becomes high if an ultra dma crc error is detected at the end of ultra dma burst. bit 2: crst - chip reset flag this bit is set high by chip reset. the first read of register miss2 (30h,r) following the end of the chip reset clears this flag to 0. bit 1: fpkt -full packet flag this bit becomes high if the host has written the number of data bytes indicated in register atblo (less than 12 bytes), or the host has written a 12-byte command packet. if cod (32h.0) is low when drq (37h.3) change from 0 to 1, the count in atblo is latched as a threshold value for fpkt logic. if cod is high when drq (37h.3) change from 0 to 1, the threshold value of fpkt logic is set as 12. whenever the number of bytes in the packet fifo equals the threshold value, flag fpkt becomes high. to receive data from host using packet fifo, cod (32h.0) and atblo (32h) should be updated at rising edge of drq. bit 0: apkt - automatic packet transfer flag this bit is set to 1 when host writes opcode a0h to ata command register if drive is selected and apkten (18h.7) has been enabled. when this flag is high, bsy is controlled by the automatic packet transfer logic. hence, setting of clrbsy (20h.4) and setbsy (20h.4) is of no effect. apkt is de-activated by writing any value to register tack (07h,w) . apkt is de-activated by chip reset or host reset but is not changed by firmware reset.
w88113c publication release date: mar. 1999 - 47 - revision 0.61 aterr - atapi error register (write 31h/read 39h) this register is set as 01h by the following events: chip reset or host reset srst execute drive diagnostics command triggering sigt (17h.w4) atfea - atapi feature register (read 31h) this register is de-activated by the following events: chip reset or host reset srst execute drive diagnostics command triggering sigt (17h.w4) atint - atapi interrupt reason register (read/write 32h) this register is set as 01h by the following events: chip reset or host reset srst execute drive diagnostics command triggering sigt (17h.w4) atspa - atapi sam tag bytes register (read/write 33h) this register is set as 01h by the following events: chip reset or host reset srst execute drive diagnostics command triggering sigt (17h.w4)
w88113c publication release date: mar. 1999 - 48 - revision 0.61 atblo - atapi byte count low (read/write 34h) this register is set as 14h by chip reset, host reset, srst or triggering sigt (17h.w4) . this register is set as 00h by execute drive diagnostics command. atbhi - atapi byte count high (read/write 35h) this register is set as ebh by chip reset, host reset, srst or triggering sigt (17h.w4) . this register is set as 00h by execute drive diagnostics command. atdrs - atapi drive select (read/write 36h) this register is set as 00h by the following: chip reset or host reset srst execute drive diagnostics command note that this register is not changed by triggering sigt (17h.w4) . atsta - atapi status register (write 37h/read 38h) this register is set as x0000000b by chip reset, host reset. this register is set as x00x0000b by srst, execute drive diagnostics command, or triggering sigt (17h.w4) .note that bsy is not changed by writing register atsta (37h). atcmd - atapi command register (read 37h) this register is used to latched the command opcode written from host without default value. assta - atapi shadow status register - (write 38h) bit 0: scheck - shadow check bit if configured as a master drive, the firmware should set scheck following each host write to atcmd to comply with atapi specification. bit-7 of shadow status register is the same as bsy of status register. bit 6-1 of shadow status register are all 0s. scheck is de- activated by chip reset, host reset, or host writes to command register regardless of which drive is selected.
w88113c publication release date: mar. 1999 - 49 - revision 0.61 aserr - atapi shadow error register - (write 39h) bit 2: sabrt - shadow abrt bit t he microprocessor should set sabrt following each host write to atcmd to comply with atapi specification if configured as a master drive. the other bits of shadow error register are all 0s.. lddbl/lddbh - latched decoded data block register - (read 3ah/3bh) the decoded data block number in ddbh/l is latched into lddbh/l at the end of edc check. this number is available to the end of next edc check. the lddbh/l shoule not be used if bicen (9ah.7) is enabled. apksta - status register for automatic packet transfer - (write 3dh) bit 4: adsc - disk seek complete for automatic packet transfer the value of adsc is the value of bit dsc in atapi status register during automatic packet command transfers. ascsta - status register for automatic status completion - (write 3eh) bit 6: adrdy - drive ready for automatic status completion the value of adrdy is the value of bit drdy in the atapi status register during automatic status completion. bit 2: acorr - correctable error for automatic status completion the value of acorr is the value of bit corr in the atapi status register during automatic status completion. corr is de-activated by chip reset, host reset, or firmware reset. bit 0: acheck - check for automatic status completion the value of acheck is the value of bit check in the atapi status register during automatic status completion. check is de-activated by chip reset, host reset, or firmware reset.
w88113c publication release date: mar. 1999 - 50 - revision 0.61 shdctl - shadow drive control register (read/write 3fh) bit 7, 4, 3: reserved bit 6: shdrv - s hadow drive enable if mdrv (2fh.4) is high, the bit reflects the level on pin daspb (43) until shdrvl (3fh.5) is set high. if this bit is high, shadow register support for the non-existent slave drive is enabled.. bit 5: shdrvl - shadow drive enable latch microprocessor should set this bit high at least 450 milliseconds after chip reset or host reset to latch the setting of shdrv (3fh.6) from pin daspb if configured as a master drive. this bit is 0 after chip reset and host reset. bit 2: dasps2 - das p select 2 setting this bit high enables daspen (20h.w5) during host reset. dasps2 should normally be 0 to comply with atapi specification. this bit is 0 after chip reset. bit 1: dasps1 - dasp select 1 setting this bit high enables daspen (20h.w5) following end of host reset. this bit is 0 after chip reset. bit 0: daspss - dasp srst select setting this bit high enables daspen (20h.w5) following the end of soft reset (srst). this bit is 0 after chip reset and host reset. lsta0 to lsta3 - latched status registers - (read 48h to 4bh) the contents of stat0-3 (0c-0fh,r) are latched into these four registers at the end of edc check. these values are available to the end of next edc check. these registers shoule not be used if bicen (9ah.7) is enabled. lhd0 to lhd3 - latched header registers - (read 4ch to 4fh) the contents of head0-3 (04-07h.r) are latched into these four registers at the end of edc check. these values are available to the end of next edc check. these registers shoule not be used if bicen (9ah.7) is enabled.
w88113c publication release date: mar. 1999 - 51 - revision 0.61 ring control registers - (read/write 50h to 57h) these eight registers add flexibility to the block control of external memory that is controlled by rtc2-0 (2ah.2-0) initially. once one of these eight registers is set, all eight registers should be set to take full control of block configuration of the external memory. the data-transfer-ring and write- buffer-ring are normally set the same value. dtrbl/dtrbh - data transfer ring base register - (read/write 50h/51h) data transfer ring base register and data transfer ring ceiling register treat the external memory as a ring while transferring data to the host. data transfer ring base register specifies the base block number of this ring. dtrcl/dtrch - data transfer ring ceiling register - (read/write 52h/53h) data transfer ring base register and data transfer ring ceiling register treat the external memory as a ring while transferring data to the host. data transfer ring base register specifies the ceiling block number of this ring. the first block to be transferred is specified by registers tbh/l (25h/24h) . the further data transfer after the end of data transfer ceiling block will access data in data transfer base block. wbrbl/wbrbh - write buffer ring base register - (read/write 54h/55h) write buffer ring base register and write buffer ring ceiling register treats the external memory as a ring while buffering the serial data from dsp. write buffer ring base register specifies the base block number of this ring. wbrcl/wbrch - write buffer ring ceiling register - (read/write 56h/57h) write buffer ring base register and write buffer ring ceiling register treats the external memory as a ring while buffering the serial data from dsp. write buffer ring base register specifies the base block number of this ring. the first block to be buffered is specified by registers ddbh/l (29h/28h) . further serial data buffering after the end of write buffer ceiling block will buffer serial data into the write buffer base block.
w88113c publication release date: mar. 1999 - 52 - revision 0.61 pskctl - programmable system clock control register - (read/write 59h) this register should be set before the programmable system clock is enabled by setting psken (1ah.w4) high. this register is 0 after chip reset. bit 7: psksel (write) - programmable sy stem clock select if this bit is high, the internal system clock will be adjusted to fit the programmed frequency according crystal input. if this bit is low, the internal system clock will be adjusted to fit the programmed frequency according to internal clock. bit 7: locked (read) - programmable system clock locked this bit is high once the internal system clock is ever on lock with the programmed frequency. bit 6: locksel (write) - programmable system clock lock select if this bit is high, the inte rnal system clock will keep the same delay path once the programmed frequency is locked. this function keeps system clock at steady frequency, but the frequency may be affected by temperature. if this bit is low, the internal system clock will be continuously adjusted to fit the programmed frequency according to crystal input and result in a various frequency. bit 6: onlock (read) - programmable system clock on lock this bit is high if internal system clock is on lock with the programmed frequency. bit 5-0: psk[5:0] - programmable system clock factor if psken (1ah.w4) and psksel (59h.w7) are high, these six bits are used to controlled the internal system frequency. the equation is: frequency system clock = frequency of xin (psk[5:0] + 2) ? 16 sctc - subcode timer control register - (write 5ah) if sbxck (2ch.w7) and cd2sc (2ch.w5) are both low, the clock used by subcode logic clock is controlled by subcs2-0 (21h.w2-0) unless any non-zero value is written into this register. the value of this register should be calculated as follows: ( n + 2 ) tc dsf = 11.3 / 2 where tc is the internal clock period(ex: 50ns for 20mhz crystal), dsf is the disk speed factor(ex: 4 for 4-fold speed drive). there is no need to set this register if sbck (88h.w3) is set high. efctl - enhanced feature control register - (read/write 5bh) bit 7: asdma - automatic set dma if this bit is high, the inverted value of dma bit of atfea (1f1h,w) will be automatically loaded to pio (1fh.2) . this bit is 0 after chip reset, host reset and firmware reset.
w88113c publication release date: mar. 1999 - 53 - revision 0.61 bit 6: asrit - alternate srib timing (obsolete function) bit 5: dsp1stb bit 4: reserved bit 3: alrt - alternate latch registers timing (obsolete function) bit 2: reserved bit 1: dra - direct register addressing enable if this bit is set high, the direct register addressing function is enabled. this bit is 1 after chip reset in normal condition. but if pin ra8 (92) is connected to a 4.7k w pull-down resister, this bit is set high after chip reset. this alternative power-on setting provides a way to do conventional indirect register addressing. bit 0: reserved power-on setting of register addressing mode the default register addressing mode of w88113cf is direct register addressing mode. alternative power-on setting ra8 pull-down 4.7k w ra7 pull-down 4.7k w direct register select ale input pin 16-bit dram support no (default) no (default) yes ale2 yes no yes yes ale1 no yes no no x yes yes yes no x no efctl2 - enhanced feature control register 2- (read/write 5ch) bit 7-4: reserved bit 3: ale2 - ale2 enable when this bit is set high, pin ale2 (64) is used as ale input. this bit is 1 after chip reset in normal condition. but if pin ra7 (93) is connected to a 4.7k w pull-low resister, this bit is set low after chip reset. bit 2: syncp - sync bytes patch enable if this bit is high, the sync bytes of the following sector are patched to the previous sector. this bit must be disabled when reading cd-da data.
w88113c publication release date: mar. 1999 - 54 - revision 0.61 bit 1: reserved bit 0: rmsri - remove frequent srib if rmsri (5ch.0) is high, flag srib (01h.r5) is generated only by flags staerr (80h.r6) , dsfuli (80h.r4) , lastbk (80h.r3) , ltti (80h.r2) , tnfi (80h.r1) or hcei (80h.r0) . setting this bit high can reduce the overhead of microcontroller while the automatic cache management is used. this bit is 0 after chip reset, host reset and firmware reset. lsubh2 - latched subheader 2 register - (read 5dh) the content of subheader-2-register(16h) is latched into this register at the end of edc check. this value is available to the end of next edc check. pskcnt - programmable system clock internal counter (read 5eh) bit 4-0 of this register hold the internal counter of programmable clock system. this value can be read for ststem debug. gioctl - general i/o port control register - (read/write 5fh) pin hrstb (21) can be configured as gio1 by hrsts1-0 (2fh.5-4) . pin arstb (60) can be configured as gio2 by arsts1-0 (2fh.3-2) . this register is 0 after chip reset. bit 7-6: reserved bit 5: g2oen - general i/o port 2 output enable setting this bit high configure gio2 as output. otherwise, it is an input pin. bit 4: g1oen - general i/o port 1 output enable setting this bit high configure gio1 as output. otherwise, it is an input pin. bit 3: reserved bit 2: gin3 - general input port 3 the pin state of urs (32) can be read back from this bit if dra (5bh.1) is high and da0en (87h.7) is low. bit 1: gio2 - general i/o port 2 if gio2 is configured as an input pin, the pin state can be read back from this bit. if gio2 is configured as an output pin, set this bit low drive gio2 low and set this bit high cause a weak pull-up. bit 0: gio1 - general i/o port 1 if gio1 is configured as an input pin, the pin state can be read back from this bit. if gio1 is configured as an output pin, set this bit low drive gio1 low and set this bit high cause a weak pull-up.
w88113c publication release date: mar. 1999 - 55 - revision 0.61 tarctl - target control register - (write 80h) this register is used to control the automatic target search and header comparison. since these control bits are not changed by closing decoder, there is no need to write it before every time the decoder is enabled. bit 7: targen - target function enable setting this bit high enables target search function but does not enable decoder simultaneously. the operation of target search is triggered by setting decen (0ah.w7) high. then the decoder generates first interrupt after the target sector, specified by target (84h- 86h) , is found. bit 6: dscen - decoding sector counting enable if dscen (80h.6) is enabled, flag dsfuli (80h.r4) becomes high if dscl (81h,r) is equal to dstl (81h,w) at the end of edc-checking. bit 5: qen - q-channel extraction enable setting this bit high enables q-channel extraction logic. this pin should be set high only when scen (2ch.w6) is high. once decoder and q-channel extraction are both enabled, the extracted q-channel bytes are written into the dram starting from offset 9e0h of each block regardless of what mode of data is set. bit 4: qmsf - q-channel msf auto-load enable if q-channel extract ion logic is enabled, setting this bit high enables the msf bytes of q- channel to be automatically loaded to head0-2 (04h-06h,r) . bit 3: astopb - automatic decoder stop on error if this bit is low, decoder would automatically stop on the following conditions: hcei (80h.r0) activates if hceen (80h.w0) is enabled. tnfi (80h.r1) activates if tnfen (80h.w1) is enabled. ltti (80h.r2) activates if ltten (80h.w2) is enabled. lastbk (80h.r3) activates if blimen (9ah.5) is enabled dsfuli (80h.r4) activates if dscen (80h.w6) is enabled. staerr (80h.r6) activates if any status mask bit is enabled if this bit is low, the consistency of f/w and h/w should be carefully maintained. if this bit is high, the decoder is controlled by microprocessor. this bit is default low after chip reset. bit 2: ltten - larger than target interrupt enable setting this bit high enables ltti (80h.r2) to be reflected on srib (01h.r5) . bit 1: tnfen - target not found interrupt enable setting this bit high enables tnfi (80h.r1) to be reflected on srib (01h.r5) . bit 0: hceen - header compare error interrupt enable setting this bit high enables hcei(80h.r0) to be reflected on srib (01h.r5) .
w88113c publication release date: mar. 1999 - 56 - revision 0.61 tarsta - target status register - (read 80h) this register is 0 after chip reset, host reset, firmware reset and decoder reset. reading this register deactivates srib (01h.r5) . bit 7: targed - target is found this bit is high after the target is found. bit 6: staerr - status error flag this bit becomes high if any status bit error, enabled by its corresponding mask bit, occurs at the end of edc-checking. this flag is deactivated after reading register tarsta (80h,r) . bit5: bin0 - block indicator is not zeror flag if bin0m (8ch.w1) is high, this bit becomes high if the block indicator in head3 (07h.r7-5) is not zero. this flag also activates staerr (80h.r5) high. bit 4: dsfuli - decoding sector full interrupt flag if dscen (80h.6) is enabled, this flag becomes high if dscl (81h,r) is equal to dstl (81h,w) at the end of edc-checking. bit 3: lastbk - last decoded block if blimen (9ah.5) is high, this bit is set when the last pre-buffered block is decoded. firmware should disable decoder when detect this flag. the dsp buffering stop when buffer- cache full. bit 2: ltti - larger than target interrupt flag if ltten (80h.w2) and targen (80h.w7) are high, this flag becomes high if the header larger than target when head0-2 (04h-06h) are available. this flag is deactivated after reading register tarsta (80h,r). bit 1: tnfi - target not founded interrupt flag this bit becomes high if the headers in head0-2 (04h-06h) never match the target after n successive comparisons. where n is the search limit number specified by tsl (83h,w ). if tnfen (80h.w1) is high, srib (01h.r5) activates when this bit becomes high. if astopb (80h.w3) is low, this event also clears decen (0ah.w7) and stop the decoder automatically. this flag is deactivated after reading register tarsta (80h,r) . the microprocessor could read out the header after event occurs to determine the distance from target. bit 0: hcei - header compare error interrupt flag after target is founded, the number in target (84h-86h) will automatically increment after head0-2 (04h-06h) are available. if the headers of following sector do not match the target, this bit becomes high and activates srib (01h.r5) if hceen (80h.w0) is enabled. it also clears decen (0ah.w7) and stop the decoder automatically if astopb (80h.w3) is low. this flag is deactivated after reading register tarsta (80h,r) .
w88113c publication release date: mar. 1999 - 57 - revision 0.61 dstl - decoding sector threshold register - (write 81h) if dscen (80h.w6) is enabled, this register specified the threshold number of successive sectors minus one to be decoded after header is targeted. flag dsfuli (80h.r4) becomes high when value in dscl (81h,r) is equal to dstl (81h,w) at the end of edc-checking. the initial value of dstl (81h,w) is ffh after chip reset, firmware reset and decoder reset. note that threshold value should not be set as 00h if dscen (80h.w6) is enabled. dsth - obsolete (write 82h) dscl - decoding sector counter - (read 81h) once the target header is found, this counter increments when a sector is completely decoded. this counter is incremental-only, and the value follows ffh is 0. if dscen (80h.6) is high, flag dsfuli (80h.r4) becomes high if dscl (81h,r) is equal to dstl (81h,w) at the end of edc-checking. meanwhile, the decoder stops if astopb (80h.w3) is low. this register is cleared to 00h at the falling edge of decen (0ah,w7) . the initial value of dscl after chip reset, firmware reset and decoder reset is 00h. dsch - obsolete (read 82h) tsl - target search limit register - (write 83h) this register specified the limited number of target search. if n is the number specified by this register, tnfi (80h.r1) becomes high if the headers have not match the target after n successive sectors. since this register will not be changed by decoding operation, there is no need to writing it before every decoding operation. the initial value of tsl after chip reset, host reset and firmware reset is ffh. tsc - target search counter - (read 83h) after the decoder is enabled, the number of sectors has been searched can be monitored by reading tsc. this register is cleared to 00h at the falling edge of decen (0ah,w7) . the initial value of tsc after chip reset, firmware reset and decoder reset is 00h.
w88113c publication release date: mar. 1999 - 58 - revision 0.61 target0 - target minute register - (read/write 84h) target1 - target second register - (read/write 85h) target2 - target frame register - (read/write 86h) dactl - digital audio control register - (read/write 87h) this register is 00h after chip reset and host reset. bit 7: da0en - digital output 0 enable if this bit is high, the digital audio data output through pin urs/da0 (32) . bit 6: ctlsel - control bit source select if this bit is high, the 4 control bits of q channel are defined by qctl3-0 (87h,3-0) . otherwise, these 4 control bits are extracted from external ram. this bit is normal set low if the q-channel extraction work properly. bit 5-4: accu[1:0] - clock accuracy these two bit s are used as clock accuracy bits in digital audio output. these two bits are usually set 00b. bit 3:0: qctl[3:0] - control bits for q channel if ctlsel (87h.6) is high, these four bits are used as q channel control bits in digital audio output. feactl - feature control register - (read/write 88h) this register is 00h after chip reset and host reset. bit 7: lecas - latch data with external cas signal if this bit is high, input dram data is latched by external cash/l signal instead of rising edge of internal clock. this function can eliminate the timing difference between dram data and its latch signal caused by various internal chip delays, depending on circumstances. this function should not be used if edoen (88h.1) is high. bit 6: lref - long refresh cycle if this bit is high, the tras is 2.5 clocks instead 1.5 clocks for refresh cycle. bit 5: mrcd - medium ras to cas delay the bit controls the timing of trcd and trp. if this bit is high the tras for ras-only refresh is 2 clocks and cas-be fore-ras is not affected (1.5 clocks). bit 4: sdbs - subcode and dsp block synchronization this bit provides block synchronization of cd-da format data. if this bit is high, the buffering of incoming serial data and subcode to the external ram will synchronize to the same block defined by ddbh/l (29h/28h) .
w88113c publication release date: mar. 1999 - 59 - revision 0.61 bit 3: sbck - select bck as subcode clock when this bit is high, the pin bck (10) is selected as subcode reference clock instead of system clock. this setting is suitable for drive using cav subco de. bit 2: cas8b - eight cas in one ras enable when this bit is set low, maximum the number of column address strobe is 8 instead of 4 in one dram fpm cycle. bit 1: frcdb - fast ras to cas delay the bit controls the timing of trcd and trp. bit 0: edoen - edo dram support enable setting this bit enables edo dram support and the data latch timing of dram changes to falling edge instead of rising edge of internal clock. dram timing setting the timing of dram is controlled by mrcd (88h.5) and frcdb (88h.1) . the slower timing may be required to support some slower drams. mrcd frcdb trcd trp tpc minimum cycle 0 0 1 t 1.5 t 1 t 3 t 0 1 2 t 1.5 t 1 t 4 t 1 0 1.5 t 1 t 1 t 3 t 1 1 x x x x where t is the system clock period. dram timing trp rasb casb trcd tpc tras
w88113c publication release date: mar. 1999 - 60 - revision 0.61 dffcntl - data fifo threshold control register - (read/write 89h) bit 7,6: reserved bit 5-3: dffht[2:0] - data fifo high threshold when the number of bytes in data fifo larger than dffht, device stops pre-fetch to prevent fifo overrun. since the defau lt setting of cas8b (88h.2) is low, the default value of dffht is 001b. dffht[2:0] threshold 000b 28 001b 24 default 011b 16 bit 2-0: dfflt[2:0] - data fifo low threshold when the number of bytes in data fifo less than dfflt, device de-activates dmarq to prevent fifo underrun in traditional dma mode. when the number of bytes in data fifo less than dfflt, device would stop issuing dstrobe to prevent fifo underrun in ultra dma data-in mode. dfflt[2:0] threshold 000b 4 default 001b 8 011b 16 atctl - auxiliary timing control register - (read/write 8ah) this register is set 00h after chip reset, host reset and firmware reset. bit 7: xoff - crystal off setting his bit high can turn off the crystal cell and save power consumption. xoff is de- activated by the following events: chip reset or host reset or firmware reset command write from the host while the drive is selected host issues diagnostic command, regardless of drive selection host issues command to shadow drive if shdrv (3fh.6) is enabled host set bit srst in atapi device control register high, regardless of drive selection bit 6: reserved.
w88113c publication release date: mar. 1999 - 61 - revision 0.61 bit 5-4: udt[1:0] - ultra dma timing control these two bits define the ultra dma timing factor, udtf , which control the timing of ultra dma transfer. tcyc = ( 2 + udtf ) tudma where tudma is clock period that depends on setting of uclks (8ah.3) and tcyc is ultra dma cycle time (from dstrobe edge to dstrobe edge) device firmware should set udtf according to the clock source and the assigned ultra dma transfer mode after host issues set feature command. if there are frequent crc errors in data-in bursts, device firmware may switch system to slower ultra dma mode by increasing udtf to improve data integrity. example : if uclks (8ah.3) is low and system clock is 33.8688mhz, the udtf should be the following value to abide by the determined ultra dma mode. ultra dma tcyc min. spec. tcyc udtf mode 0 114 ns 118 ns 2 mode 1 75 ns 88.6 ns 1 mode 2 55 ns 59 ns 0 bit 3: uclks - ultra dma clock select if this bit is high, the clock source for udma is from pin aclk (46). if this bit is low, the clock source is system clock. bit 2-0: reft[2:0] - refresh timing control the frequency of refresh is controlled by reft2-0 (8ah.2-0) to support long refresh. the value after chip reset is 0. the refresh cycle defaults to be issued once after 256 system clocks. refresh period = 256 2reft system clock periods sta0m - status 0 mask register - (write 8ch) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 7 - crcok mask bit 6 - ilsync mask bit 5 - nosync mask bit 4 - lblk mask bit 3 - wshort mask bit 2 - sblk mask bit 1 - bin0 mask bit 0 - uceblk mask
w88113c publication release date: mar. 1999 - 62 - revision 0.61 sta1m - status 1 mask register - (write 8dh) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 4: hdera mask bit 0: shder mask sta2m - status 2 mask register - (write 8eh) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 2: nocor mask bit 1: rfomr1 mask sta3m - status 3 mask register - (write 8fh) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 5: cblk mask bit 4: eccinc mask bit 1: c2blk mask apcnf - audio playback configuration register - (read/write 90h) the default value of this register is 00h after chip reset, host reset and firmware reset. bit 7: apen - audio playback enable setting this bit high enables audio playback logic. once audio playback logic is enabled, the buffered data will be sent out block after block starting from the setting of apbk (92h/93h) . the playback stops immediately and keeps "mute" once this bit is set low. bit 6: apien - audio playback interrupt enable setting this bit high enables audio-playback-interrupt to be reflected on pin uintb (36) whenever each block playback is finished. audio-playback-interrupt flag is reflected on apib (01h.r2) if apout1-0 (90h,1-0) is not zero.
w88113c publication release date: mar. 1999 - 63 - revision 0.61 bit 5: apdirect - audio direct playback setting this bit high directs the original dsp signals to the audio playback pins. bit 4: apins - audio reference input select if this bit is set low, pin aclk (46) is used as audio-playback reference clock. if this bit is high, system clock is used as audio-playback reference block. bit 3,2: apin[1:0] - audio input reference clock setting apin[1] apin[0] input reference clock 0 0 8.4672mhz 0 1 16.9344mhz 1 0 33.8688mhz 1 1 67.7376mhz the value in these registers should be properly set according to the audio-playback reference clock before enable apen (90h.7). bit 1,0: apout[1:0] - audio data output setting apout[1] apout[0] audio data output pin pin 6 pin 13 0 0 no output tri-state clko 0 1 roeb/asd1(84) 1 0 asd0(58) abck alrck 1 1 rd8/asd2(86) when apout1-0 are set zero, no output is generated from pin abck (6) and pin clko/alrck (13) is used as left-right clock output. when apout1-0 are set not zero, flag apib (01h.r2) becomes low whenever one block audio-playback is finished. setting apic (99h.0) high tri-state the associated audio-playback output pin, including alrck, abck and adat, with weak pull-up. apfmt - audio playback format register - (read/write 91h) apfmt7-0 audio data format 000xx111h toshiba 001xx100h sanyo 101xx011h sony 48-bit slot 110xx011h philip
w88113c publication release date: mar. 1999 - 64 - revision 0.61 apfmt4 apfmt3 functions 0 0 normal stereo 0 1 mono right 1 0 mono left 1 1 left/right swap 11 10 9 8 7 6 5 4 3 2 1 0 0 15 14 13 12 15 l=lch toshiba audio format apfmt(91h) = 07h alrck abck adat 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 15 h=lch sanyo audio format apfmt(91h) = 24h 0 alrck abck adat 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 15 h=lch sony audio format apfmt(91h) = a3h 0 alrck abck adat l=lch philips audio format apfmt(91h) = c3h alrck abck adat 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 15 apbkl/h - audio playback block register - (read/write 92h/93h) the bit-0 of apbkh (93h) and bit7-0 of apbkl (92h) form a 9-bit counter. the value in this 9-bit counter defines the first block to be playbacked when apen (90h.7) is enabled. the value in these registers is incremented by 1 after one block playback is finished. 93h.bit-4: bufcwen - bufc write enable (obsolete)
w88113c publication release date: mar. 1999 - 65 - revision 0.61 apwcl/h - audio playback word count register - (read/write 94h/95h) the number in this counter plus one is the word count to be playbacked for each memory block. the default value of these registers is 0497 h after chip reset, host reset and firmware reset. no need to change this value for normal usage. apvol - audio playback volume register - (read/write 96h) bit 7-4: lvol[3:0] - left channel volume control bit 3:0: rvol[3:0] - right channel volume control lvol3-0/rvol3-0 binary number attenuation (db) fh ffh 0 (on) eh f0h -0.56 dh e0h -1.16 ch c0h -2.50 bh 80h -6.00 ah 40h -12.0 9h 20h -18.0 8h 10h -24.0 7h 0fh -24.6 6h 0eh -25.2 5h 0ch -26.6 4h 08h -30.0 3h 04h -36.0 2h 02h -42.1 1h 01h -48.0 0h 00h mute (off) apack - audio playback interrupt acknowledge - (write 97h) writing any value to this register deactivates flag apib (01h.r2) and its corresponding interrupt.
w88113c publication release date: mar. 1999 - 66 - revision 0.61 puctl - pull up resistor control register - (write 98h) this register is used to control the utilization of two pull-up resistors on io cells. default value is 0. bit 7-6: hip[1:0] - host interface pull-up control setting these two bits low control two pull-up resistors of host interface i/o cells respectively. if these two bits are both high, no pull-up resistors exist. note that dd7 is controlled by dd7upb (98h.1) separately, bit 5-4: uip[1:0] - microprocessor interface pull-up control setting these two bits low control two pull-up resistors of up interface i/o cells respectively. if these two bits are both high, no pull-up resistors exist. bit 3-2: rip[1:0] - ram interface pull-up control setting these two bits low control two pull-up resistors of ram interface i/o cells respectively. if these two bits are both high, no pull-up resistors exist. bit 1: dd7upb - dd7 pull-up enable setting this bit low disable the internal pull-up resister on the pin dd7 (74) . bit 0: apipb - audio playback interface pull-up control setting this bit low enable the internal pull-up of the audio-playback output pin, including alrck, abck and adat. sictl - sink current control register - (write 99h) - obsolete
w88113c publication release date: mar. 1999 - 67 - revision 0.61 bicctl - buffer independent correction control register - (read/write 9ah) this register is 0 after chip reset, host reset and firmware reset. bit 7: bicen - buffer independent correction enable if this bit is high, the buffer-independent-correction (bic mode) is enabled. otherwise, the real-time-correction (rtc mode) is enabled. bit 6: atmsen - automatic mode switch if this bit is high, the decoder automatically change from disk-monitor mode to the pre-set buffer-mode after the target is found. bit 5: blimen - buffer limit enable if blimen (9ah.5) is high, the buffering of dsp data stops when the condition defined by blims (9ah.4) is met. this function should be enabled if bicen (9ah.7) is set high. bit 4: blims - buffer limit source select if blims (9ah.4) is high, the buffering stop when bufc (9bh,r) reach buflim (9bh,w) . if blims (9ah.4) is low, the buffering stop when buffering block (internal) reach tbh/l (24h/25h,r) minus 1. bit 3-0: rclim[3:0] - repeat correction limit if bicen (9ah.7) is high, these four bits specify the maximum number of repeat correction. buflim - buffer limit register - (write 9bh) this register is used as buffer limit when blims (9ah.4) is high. if bufcwen (92h.w4) is low, this register can be set the buffer-ring size minus n , where n is larger than 1. this register is 0 after chip reset, host reset and firmware reset. in normal operation, this register only needs to be set once after power-on. bufc - buffer counter - (read 9bh) this counter increments when a sector is buffered into external ram. if acmen (9ch.6) is high, bufc (9bh,r) decrements at the end of each data-in block transfer unless the value is zero. the value follows 0 is 0. the transfer of working area data should be implemented as linear transfer to prevent extra decrement of this counter. if acmen (9ch.6) is high, bufc (9bh,r) minus n right after skipc (9eh) is set n . this function can be used to implement the cache-partial-hit event. if both blimen (9ah.5) and blims (9ah.4) is high, the buffering stop when this count reaches buflim (9bh,w) . the value in bufc (9bh,r) may exceed buflim (9bh,w) by one. this counter is synchronized to tcc (9dh) whenever decen (0ah.w7) is low. this counter is 0 after chip reset, host reset and firmware reset.
w88113c publication release date: mar. 1999 - 68 - revision 0.61 acctl - automatic cache control register - (read/write 9ch) this register is 0 after chip reset, host reset and firmware reset. bit 7: atten - automatic transfer trigger enable the control bit adtt (17h.w2) is automatically set high if all the following conditions are met: atten (9ch.7) is high tcc (9dh) is not zero ttc (9fh) is not zero bit 6: acmen - automatic cache management enable if acmen (9ch.6) is high, the following functions are enabled: tbkh/l (25h/24h) increments at the end of each data-in block transfer tcc (9dh) and ttc (9fh) decrements at the end of each data-in block transfer tcc (9dh) minus n and tbkh/l (25h/24h) plus n right after skipc (9eh) is set n if acmen (9ch.6) is high and ttc (9fh) is not zero, the following functions are executed when adtt (17h.w2) is triggered: mbc4-0 (12h.4-0) ? min{ atlim (9ch.4-0) , tcc (9dh) , ttc (9fh) } minus 1 atbhi/lo (35h/34h) ? (mbc4-0 + 1) (twch/l + 1) x 2 if stwcen (18h.3) is high registers skipc (9eh) and ttc (9fh) are stuck at 0 if acmen (9ch.6) is low. bit 5: tcincen - transfer cache increment enable when this bit is high, the tcc (9dh) increments at the end of edc-checking if there is no staerr (80h.r6) or hcei (80h.r0) error. this bit should be high if tcc (9dh) is used to implement cache management. bit 4-0: atlim[4:0] - automatic transfer block limit if acmen (9ch.6) is high and tcc (9fh) is not zero, these five bits specify the maximum number of blocks that can be transferred to host in one trigger. the minimum limit is 1. setting 0 to these bits specify limit as 32 blocks. tcc - transfer cache counter - (read/write 9dh) this counter can be used to implement cache management if rmsri (5ch.0) is high. if tcincen (9ch.5) is high, tcc (9dh) increments at the end of edc-checking if there is no staerr (80h.r6) or hcei (80h.r0) error. if acmen (9ch.6) is high, tcc (9dh) decrements at the end of each data-in block transfer unless the value is zero. the value follows 0 is 0. the transfer of working area data should be implemented as linear transfer to prevent extra decrement of this counter. if acmen (9ch.6) is high, tcc (9dh) minus n right after skipc (9eh) is set n . this function can be used to implement the cache-partial-hit event. this register is 0 after chip reset, host reset and firmware reset. this counter should be set 0 in cache-miss case. writing this register should be prevented when the decoder is on or the data-in transfer is in progress.
w88113c publication release date: mar. 1999 - 69 - revision 0.61 skipc - skip count - (read/write 9eh) this register is used as skip count to implement a partial-hit event of transfer cache. if acmen (9ch.6) is high, the following functions are executed right after skipc (9eh) is set n : bufc (9bh,r) minus n tcc (9dh) minus n tbh/l (25h/24h) plus n skipc (9eh) minus n after execution of the above operations, the value in skipc (9eh) is 0. this register is 0 after chip reset, host reset and firmware reset. this register is stuck at 0 if acmen (9ch.6) is low. ttc - total transfer count - (read/write 9fh) this register is used as total transfer count. if acmen (9ch.6) is high, ttc (9fh) decrements at the end of each data-in block transfer unless the value is zero. the value follows 0 is 0. the following events are generated at the end of data-in transfer only if tcc (9fh) is zero: tendb (01h.r6) ? 0 automatic status complete sequence if ascen (18h.5) is enabled this register is 0 after chip reset, host reset and firmware reset. this register is stuck at 0 if acmen (9ch.6) is low.
w88113c publication release date: mar. 1999 - 70 - revision 0.61 3. register table note that this table is msb leading. index type name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - r/w ir index 00h r pfar b7 b6 b5 b4 b3 b2 b1 b0 01h w intctl pfneen tenden srien 0 0 0 dten x 01h r intrea pfne tend srib hcib tbsyb apib dfrdyb scib 02h r/w twcl b7 b6 b5 b4 b3 b2 b1 b0 03h w twch latxf 0 0 0 b11 b10 b9 b8 03h r twch latxf latxf latxf latxf b11 b10 b9 b8 04h w tacl a7 a6 a5 a4 a3 a2 a1 a0 05h w tach a15 a14 a13 a12 a11 a10 a9 a8 06h w thtrg data unused 07h w tack data unused 04h r head0 header minutes (bcd) 05h r head1 header second (bcd) 06h r head2 header frames (bcd) 07h r head3 header mode (bcd) 08h w bial a7 a6 a5 a4 a3 a2 a1 a0 09h w biah a15 a14 a13 a12 a11 a10 a9 a8 08h r eial a7 a6 a5 a4 a3 a2 a1 a0 09h r eiah a15 a14 a13 a12 a11 a10 a9 a8 0ah w ctrl0 decen rtedc edcen acen x bufen qcen pcen 0bh w ctrl1 sien sden dscren cwen m2rq f2rq mcrq shden 0ah r bacl a7 a6 a5 a4 a3 a2 a1 a0 0bh r bach a15 a14 a13 a12 a11 a10 a9 a8 0ch w eial a7 a6 a5 a4 a3 a2 a1 a0 0dh w eiah a15 a14 a13 a12 a11 a10 a9 a8 0ch r stat0 crcok ilsyn nosyn lbkf wshort sbkf 0 uceblk 0dh r stat1 bi2 bi1 bi0 hdera 0 0 0 shdera 0eh w dhtack data unused 0eh r stat2 rmod3 rmod2 rmod1 rmod0 mode2 nocor rfera rform 0fh w frst data unused 0fh r stat3 stavab 0 ecf 0 0 0 c2df 0 10h w ctrlw 0 swen sdss dcken 0 c2wen drst 0 11h w crtrg data unused crrl 12h w mbtc0 0 0 0 mbc4 mbc3 mbc2 mbc1 mbc0 12h r mbtc0 mbvab mbinc 0 mbc4 mbc3 mbc2 mbc1 mbc0 13h r/w mbtc1 0 0 0 0 0 mbtien mbtfen incmbc 14h w ectrl 0 0 0 0 0 0 ir7f disai 14h r subho subheader(file) 15h r subh1 subheader(channel) 16h r subh2 subheader(submode) 17h r subh3 subheader(coding)
w88113c publication release date: mar. 1999 - 71 - revision 0.61 17h w astrg 0 csrt dsct sigt cpft adtt drqt sct 18h r/w asctrl apkten adcen ascen autoen stwcen aucrcen abyen pktien 19h w cctl0 ckstp x jpss 0 csk3 csk2 cks1 csk0 1ah w cctl1 clkoen tsync xininv psken clk1 clk0 0 xtald2 1ah r ver e6h 1bh w dspsl c2ml s16o lchp sft8 0 sel16 dir edge 1bh r c2beb b7 b6 b5 b4 b3 b2 b1 b0 1ch w racl a7 a6 a5 a4 a3 a2 a1 a0 1dh w rach a15 a14 a13 a12 a11 a10 a9 a8 2dh w racu 0 0 0 0 a19 a18 a17 a16 1eh w ramwr b7 b6 b5 b4 b3 b2 b1 b0 1eh r ramrd b7 b6 b5 b4 b3 b2 b1 b0 1fh w hictl0 x x x laen mdma pio dinb udma 1fh r stat5 utby 0 0 0 mdma pio dinb udma 20h r/w hictl1 0 pdiagen daspen clrbsy setbsy scod rdyen io16en 21h w sictl0 0 0 0 0 pqenb subcs2 subcs1 subcs0 22h w sciack data unused 22h r substa x x x qcrcok x mss nesbk iss 24h r/w tbl b7 b6 b5 b4 b3 b2 b1 b0 25h r/w tbh data unused b8 26h r/w scbl b7 b6 b5 b4 b3 b2 b1 b0 27h r/w scbh data unused b8 28h r/w ddbl b7 b6 b5 b4 b3 b2 b1 b0 29h r/w ddbh data unused b0 2ah w ramcf rftyp rftrg x swap b3 rtc2 rtc1 rtc0 2ah r ramcf rftyp rftrg rfc swap b3 rtc2 rtc1 rtc0 2bh w memcf slts1 dlts0 dbaf1 dbaf0 dfrst frdy rlc1 rlc0 2ch w sictl1 sbxck scen cd2sc scien exinv exop scf1 scf0 2eh w misc0 hiien 0 drveb mdrv hirq 0 0 0 2eh r miss0 1 1 srub mdrvf hintf 1 pdiagb daspb 2fh w misc1 arrc sarrc hrsts1 hrsts0 arsts1 arsts0 arstien arwc 2fh r miss1 srst atac diag shdc arst rst frst hrst 30h w arstack data unused 30h r miss2 srstd cmdc tdir mbti ucrcokb crst fpkt apkt 31h w aterr b7 b6 b5 b4 mcr abrt eom ili 31h r atfea 0 0 0 0 0 0 0 dma 32h r/w atint 0 0 0 0 0 0 io cod 33h r/w atspa 0 0 0 0 0 0 0 1 34h r/w atblo b7 b6 b5 b4 b3 b2 b1 b0 35h r/w atbhi b7 b6 b5 b4 b3 b2 b1 b0 36h r/w atdrs 1 l 1 drv 0 0 0 0 37h w atsta 0 drdy 0 dsc drq corr 0 check 37h r atcmd b7 b6 b5 b4 b3 b2 b1 b0 38h w aserr 0 0 0 0 0 0 0 scheck 38h r aterr bsy drdy b5 dsc drq corr 0 check
w88113c publication release date: mar. 1999 - 72 - revision 0.61 39h w aserr 0 0 0 0 0 sabrt 0 0 39h r aterr b7 b6 b5 b4 mcr abrt eom ili 3ah r lddbl latched ddbl 3bh r lddbh latched ddbh 3dh w apksta 0 0 0 adsc 0 0 0 0 3eh w ascsta 0 adrdy 0 0 0 acorr 0 acheck 3fh r/w shdctl 0 shdrv shdrvl 0 0 dasps2 dasps1 daspss 48h r lsta0 crcok ilsyn nosyn lbkf wshort sbkf 0 uceblk 49h r lsta1 0 0 0 hdera 0 0 0 shdera 4ah r lsta2 rmod3 rmod2 rmod1 rmod0 mode2 nocor rfera rform 4bh r lsta3 0 0 ecf 0 0 0 c2df 0 4ch r lhd0 latched header minutes (bcd) 4dh r lhd1 latched header second (bcd) 4eh r lhd2 latched header frames (bcd) 4fh r lhd3 latched header mode (bcd) 50h r/w dtrbl b7 b6 b5 b4 b3 b2 b1 b0 51h r/w dtrbh data unused b8 52h r/w dtrcl b7 b6 b5 b4 b3 b2 b1 b0 53h r/w dtrch data unused b8 54h r/w wbrbl b7 b6 b5 b4 b3 b2 b1 b0 55h r/w wbrbh data unused b8 56h r/w wbrcl b7 b6 b5 b4 b3 b2 b1 b0 57h r/w wbrch data unused b8 58h r/w reserved 59h r psksta locked onlock psk5 psk4 psk3 psk2 psk1 psk0 59h w pskctl psksel locksel psk5 psk4 psk3 psk2 psk1 psk0 5ah w sctc d7 d6 d5 d4 d3 d2 d1 d0 5bh r/w enctl1 asdma asrit dsp1stb b4 alrt b2 dra b0 5ch r/w enctl2 x x x x ale2 synp b1 rmsri 5dh r lsubh2 latched submode number 5eh r pskcnt x x x pskcnt4 pskcnt3 pskcnt2 pskcnt1 pskcnt0 5fh r/w gioctl x x g2oen g1oen x gin3 gio2 gio1 80h w tarctl targen dscen qen qmsf astopb ltten tnfen hceen 80h r tarsta targed staerr bin0 dsfuli lastbk ltti tnfi hcei 81h w dstl b7 b6 b5 b4 b3 b2 b1 b0 81h r dscl b7 b6 b5 b4 b3 b2 b1 b0 83h w tsl b7 b6 b5 b4 b3 b2 b1 b0 83h r tsc b7 b6 b5 b4 b3 b2 b1 b0 84h r/w target0 target minute (bcd) 85h r/w target1 target second (bcd) 86h r/w target2 target fram (bcd) 87h r/w dactl da0en ctlsel acu1 acu0 qctl3 qctl2 qctl1 qctl0 88h r/w feactl lecas lref mrcd sdbs sbck cas8b frcdb edoen 89h r/w dffcntl 1 1 ffht2 dffht1 dffht0 dfflt2 dfflt1 dfflt0 8ah r/w atctl xoff x udt1 udt0 uclks reft1 reft1 reft0
w88113c publication release date: mar. 1999 - 73 - revision 0.61 8ch w sta0m crcokm ilsynm nosynm lblkm wshortm sblkm bin0m uceblkm 8dh w sta1m 0 0 0 hderam 0 0 0 shderam 8eh w sta2m 0 0 0 0 0 nocorm rferam 0 8fh w sta3m 0 0 cblkm 0 0 0 c2blkm 0 90h r/w apcnf apen apien apdirect apins apin1 apin0 apout1 apout0 91h r/w apfmt apfmt7 apfm6 apfmt5 apfmt4 apfmt3 apfmt2 aptm1 apfmt0 92h r/w apbkl b7 b6 b5 b4 b3 b2 b1 b0 93h r/w apbkh aptest aptest 0 0 0 0 0 b8 94h r/w apwcl 97h 95h r/w apwch 04h 96h r/w apvol lvol3 lvol2 lvol1 lvol0 rvol3 rvol2 rvol1 rvol0 97h w apack data unused 98h w puctl hip1 hip0 uip1 uip0 rip1 rip0 hd7upb apipb 99h w sictl hic1 hic0 uic1 uic0 ric1 ric0 x apic 9ah r/w bicctl bicen atmsen blimen blims rclim3 rclim2 rclim1 rclim0 9bh w buflim b7 b6 b5 b4 b3 b2 b1 b0 9bh r bufc b7 b6 b5 b4 b3 b2 b1 b0 9ch r/w acctl atten acmen tcincen atlim4 atlim3 atlim2 atlim1 atlim0 9dh r/w tcc b7 b6 b5 b4 b3 b2 b1 b0 9eh r/w skipc b7 b6 b5 b4 b3 b2 b1 b0 9fh r/w ttc b7 b6 b5 b4 b3 b2 b1 b0
w88113c publication release date: mar. 1999 - 74 - revision 0.61 4. characteristics (t a = 0 c to 70 c, v dd = 5v 5%, v ss = 0v) sym parameter min max unit condition v oh output high voltage 2.4 v i oh =400 m a v ol output low voltage 0.4 v i ol =6 or 12ma (note 1) v ih1 input high voltage 0.7 vdd vdd+0.5 v ud[7:0], dd[15:0], rd[15:0], daspb, pdiagb, exck v il1 input low voltage -0.5 0.3 vdd v v ih2 input high voltage 2 vdd+0.5 v lrck, sdata, bck, c2po, scsd, wfck, scsyn, hrstb, urs, urdb, uwrb, ucsb, cs3b, cs1b, da[2:0], dmackb, hrdb, hwrb, crstb v il2 input low voltage -0.5 0.8 v i li1 input leakage current -10 10 m a i li2 input leakage current -130 -400 m a pins with pullup resistor at pad = 0v (notes 3) i lo1 output leakage current -10 10 m a i lo2 output leakage current -130 -400 m a pins with pullup resistor at pad = 0v (notes 3) notes: 1. output current (iol) capabilities: 6ma: ras, cash, casl, ra[8:0], rweb, roeb, clko, ud[7:0], rd[15:0], pdiagb, abck, adat, arstb, hrstb 16ma: dd[15:0], daspb, hirq, dmarq, uintb, exck, iordy, iocs16b 2. the chip contains internal resistance between xin and xout 3. the chip contains internal pullup resistance between vdd and the following pins: input: ha[2:0], dmackb, hrdb, hwrb, cs1b, cs3b output: roeb, uintb bi-directional: dd[15:0], rd[15:0], ud[7:0], daspb, pdiagb, exck, hrstb, arstb
w88113c publication release date: mar. 1999 - 75 - revision 0.61 5. application notes 5. 1 dram interface 5. 1 .1 memory layout the whole dram can be divided into sector data area and working area . sectors from dsp are buffered into sector data area and then are retrieved for ecc/edc operation. some information is stored in working area for transfer to host on request, for example, toc. sector data buffering is a block-based ring operation. if the decoded-block-number in ddbh/l (29h/28h) is n - 1 , the sector is buffered into block with number n . the decoded-block-number is automatically incremented by one at each sync. when the decoded-block-number equals the value in wbrch/l (57h/56h) , the sector is buffered into the block with number specified by wbrbh/l (55h/54h) . the data transfer is also a block-based ring operation if multi-block-transfer is used. the transfer ring is controlled by dtrch/l (53h/52h) and dtrbh/l (51h/50h) . the buffer ring and transfer ring are usually defined in the same range. ring ceiling ring base working area sector data area block number wrap around block size is a00h if rlc=3 or c00h if rlc=2 ring ceiling = 2fh ring base = 00h block #2fh block #00h block #2dh block #01h 1ffffh 1e000h 1d600h 00000h 00a00h 01400h example: 128k x 8, rlc[1:0](2bh.1-0) = 3 illustration diagram for memory layout
w88113c publication release date: mar. 1999 - 76 - revision 0.61 5. 1 .2 block configuration the configuration of each memory block depends on the data format. the following figures show the recommended configuration of block whose size is a00h and c00h, respectfully. user data (2048) ecc(276) edc(4) blank(8) unused (96) subcode (96) unused (16) header (4) sync (12) 000h 800h 920h 980h 9e0h 9f0h 9ffh configuration for mode 1 format user data (2352) unused (80) subcode (96) q-channel (12) unused (20) 000h 930h 980h 9e0h 9ech 9ffh configuration for cd-da format user data (2048) ecc(276) edc(4) unused (104) subcode (96) header (4) subheader (8) sync (12) 000h 800h 918h 980h 9e0h 9e8h 9ffh configuration for m2f1 format rlc[1:0](2bh.1-0) = 3 ecc(276) edc(4) blank(8) unused (96) subcode (96) header (4) sync (12) 000h 800h 920h 980h 9e0h bf0h bffh configuration for mode 1 format user data (2352) unused (80) subcode (96) q-channel (12) 000h 930h 980h 9e0h 9ech bffh configuration for cd-da format ecc(276) edc(4) unused (104) subcode (96) header (4) subheader (8) sync (12) 000h 800h 918h 980h 9e0h be8h bffh configuration for m2f1 format c2(294) 9feh b24h c2(294) 9feh b24h c2(294) b24h 9feh user data (2048) user data (2048) rlc[1:0](2bh.1-0) = 2
w88113c publication release date: mar. 1999 - 77 - revision 0.61 the rule for configuration is that the first byte of the sector is stored at: biah/l(09h/08h,w) - 0ch and the following byte is stored into the incremented offset address. if the offset address reaches the block limit, the next offset address is wrap around to zero. for example, the byte following that at offset 9ffh is at 000h if block limit is a00h. by this mechanism and following example settings, the first byte of user data is always located at 000h. the c2 flag (9feh), subcode (980h) and q-channel (9e0h) data are stored at fixed address if its associated function is enabled. but the 2352 bytes sector data (including sync, header, user data, ecc, edc for mode 1 sector) can be re-arranged to any other area in the block. buffering & decoding setting example the block for buffering and decoding function is set by ddbh/l (29h/28h). cd-da yellow book mode 1 & mode 2 cd-rom xa mode 2 biah/l(08h/09h) 000ch fffch fff4h first sync n/a fff0h ffe8h first header n/a fffch fff4h first subheader n/a n/a fff8h first data 0000h 0000h 0000h data transfer setting example the block for data transfer function is set by tbh/l (25h/24h). mode 1 mode 2 cd-da transfer bytes 2048 2352 2048 2352 2352 tach/l(05h/04h) 0000h fff0h 0000h ffe8h 0000h twch/l(03h/02h) 03ffh 0497h 03ffh 0497h 0497h
w88113c publication release date: mar. 1999 - 78 - revision 0.61 5. 1 .3 linear address v.s. block-offset address the microprocessor can write/read external ram through register rawr/ramrd (1eh) based on linear address defined by racu/h/l (2dh/1dh/1ch,w) . but the operation of data transfer from dram to host can base on block-offset address or linear address. the following equation defines the relation between these two types of address. linear address = (block number block size) + address offset data transfer in working area conditions: 64 bytes of toc data are stored starting from linear address 3ea00h at disc initialization and toc is requested by host (block size is a00h). a) sequence at disc initialization: a) set racl (1ch) as 00h b) set rach (1dh) as eah c) set racu (2dh) as 03h d) wait utby (1fh.7) low e) write data to register ramwr (1eh) f) goto step e) until all 64 bytes are written to dram b1) setting for block-offset address transfer: - set tbh/l (25h/24h) as 0064h - set tach/l (05h/04h) as 0200h - set twch/l (03h/02h) as 001fh b2) setting for linear address transfer: - set racl (1ch) as 00h - set rach (1dh) as eah - set racu (2dh) as 03h - set twch/l (03h/02h) as 801fh data transfer in user area conditions: mode 1 data. the block number read from register ddbh/l (29h/28h) is 1fh. case 1: the 2048 bytes of user data are requested by host. set tbh/l (25h/24h) as 001fh set twch/l (03h/02h) as 03ffh set tach/l (05h/04h) as 0000h case 2: the 288 bytes of edc&ecc data are request by host. set tbh/l (25h/24h) as 001fh
w88113c publication release date: mar. 1999 - 79 - revision 0.61 set twch/l (03h/02h) as 008fh set tach/l (05h/04h) as 0800h case 3: the 2352 bytes of sync, header, user data and edc&ecc are request by host. set tbh/l (25h/24h) as 001fh set twch/l (03h/02h) as 0497h set tach/l (05h/04h) as fff0h if the requested data is not stored continuously in dram, e.g. , header and edc&ecc data, more than one transfer has to be triggered. 5. 1 .4 16-bit dram high dram bandwidth is the key issue to support high disk speed and can be dramatically by using 16-bit dram. the following setting should be made at initialization to utilize 16-bit dram. the control bit ale2 (5ch.3) should be set high (default after chip reset). the value of rtc2-0 (2ah.2-0,w) should be 101 b (9 col) or 100 b (8 col). the ring control registers (50h-57h) should also be set to fully utilize the dram space. since dram access is based on linear addressing, there is no need of further firmware change. 5. 1 .5 edo dram edo dram is designed to improve the dram read performance. the edo dram support is enabled by setting control bit edoen (88h.w0) high. when this bit is set high, the data latch timing of dram changes to falling edge instead of rising edge of internal clock. the timing of dram is controlled by mrcd (88h.w5) and frcdb (88h.w1) . the slower timing may be required to support some slower drams. mrcd frcdb trcd trp tpc minimum cycle 0 0 1 t 1.5 t 1 t 3 t 0 1 2 t 1.5 t 1 t 4 t 1 0 1.5 t 1 t 1 t 3 t 1 1 x x x x note: t is the system clock period.
w88113c publication release date: mar. 1999 - 80 - revision 0.61 dram timing trp rasb casb trcd tpc tras 5. 2 microcontroller interface 5. 2 .1 direct register addressing the default register addressing mode of w88113cf is direct register addressing mode. if ale2 (5ch.3) is low, pin rd12/ale1 (5) is used as ale input; otherwise, pin ale2 (64) is used as ale input (default after chip reset). alternative power-on setting ra8 pull-down 4.7k w ra7 pull-down 4.7k w direct register select ale input pin 16-bit dram support no (default) no (default) yes ale2 yes no yes yes ale1 no yes no no x yes yes yes no x no addr data ale ucsb urd/uwr
w88113c publication release date: mar. 1999 - 81 - revision 0.61 5. 2 .2 general i/o pin hrstb (21) and pin arstb (60) can be configured as general i/o pins through register misc1 (2fh,w) . the state of these two general i/o pins can be controlled through register gioctl (5fh) . the pin state of urs (32) can be read back from gin3 (5fh.r2) if dra (5bh.1) is high and da0en (87h.7) is low. 5. 2 .3 programmable system clock the internal system frequency is controlled by cctl1 (1ah,w) and pskctl (59h,w) . register pskctl (59h,w) should be set before the programmable system clock is enabled by setting psken (1ah.w4) high. if both psken (1ah.w4) and psksel (59h.w7) are high, psk5-0 (59h.5-0) are used to controlled the internal system frequency. register pskctl (59h,w) should be set before the programmable system clock is enabled by setting psken (1ah.w4) high. the equation is: frequency system clock = frequency of xin (psk[5:0] + 2) ? 16 the variation of the resultant system frequency is normally less than 5%. if the frequency of pin xin (15) is 33.8688 mhz, psken (1ah.w4) and psksel (59h.w7) are high: psk5-0 system frequency 0fh 36 mhz 11h 40.2 mhz 13h 44.4 mhz 15h 48.7 mhz 17h 53 mhz 19h 57.2 mhz 1bh 61.4 mhz if the frequency of pin xin (15) is 24 mhz, psken (1ah.w4) and psksel (59h.w7) are high: psk5-0 system frequency 14h 33 mhz 16h 36 mhz 18h 39 mhz 1ah 42 mhz 1ch 45 mhz 1eh 48 mhz 20h 51 mhz
w88113c publication release date: mar. 1999 - 82 - revision 0.61 xin=33.86mhz, pskctl (59h) = d3h, cctl1 (1ah) = 98h xin=33.86mhz, pskctl (59h) = d5h, cctl1 (1ah) = 98h
w88113c publication release date: mar. 1999 - 83 - revision 0.61 5. 3 host interface the host interface is a standard atapi interface with enhanced ultra dma support. the ultra dma protocol could double the current burst transfer rate of 16.6mb/sec to 33mb/sec without hardware changes such as termination devices or different cabling. 5. 3 .1 ultra dma mode setting this decoder is capable of supporting ultra dma mode 2. device firmware could claim that ultra dma mode 2 and below are supported in identify device information. once ultra dma is enabled, the ultra dma burst is defined as the period from an assertion of dmackb to the subsequent negation of dmackb. three pins in the following table are re-defined during an ultra dma burst. value of register 1fh pio/dma ultra dma data-in x9h ultra dma data-out xbh pin 49 iordy dstrobe ddmardyb pin 50 hrdb hdmardyb hstrobe pin 52 hwrb stop stop the value of udt1-0 (8ah,5-4) defines the ultra dma timing factor, udtf , which control the timing of ultra dma transfer. tcyc = ( 2 + udtf ) tudma where tudma is clock period that depends on uclks (8ah.3) and tcyc is ultra dma cycle time ( from dstrobe edge to dstrobe edge) device firmware should set udtf according to the clock source and the assigned ultra dma transfer mode after host issues set feature command. if there are frequent crc errors in data-in bursts, device firmware may switch system to slower ultra dma mode by increasing udtf to improve data integrity. example : if uclks (8ah.w3) is low and system clock is 33.8688mhz, the udtf should be the following value to abide by the determined ultra dma mode. ultra dma tcyc min. spec. tcyc udtf mode 0 114 ns 118 ns 2 mode 1 75 ns 88.6 ns 1 mode 2 55 ns 59 ns 0 5. 3 .2 ultra dma data-out the programming of ultra dma transfer is similar to that of multi-word dma transfer. one thing should be noted is that device should prepare to receive one additional word at the end of a data out burst . since 12-byte packet fifos are used to receive data in ultra dma data-out transfer, the value
w88113c publication release date: mar. 1999 - 84 - revision 0.61 of registers twch/l (03h/02h) should be set 4 instead of 5. then firmware should repeatedly read register pfar (00h,r) after transfer end interrupt asserts until flag pfneb (01h.r7) becomes one. data-out transfer sequence: 1. tenden (01h.w6) ? 1 2. asctrl (18h,w) ? 58h 3. hictl0 (1fh.w) ? 0bh // udma data-out 4. twc (03h/02h,w) ? min(0004h, byte_cnt/2-1) 5. adtt (17h.w2) ? 1 // automatic data transfer trigger 6. wait tendb (01h.r6) = 0 and tdir (30h.r5) = 1 and fpkt (30h.r1) = 1 7. tack (07h,w) ? ffh 8. read pfar (00h,r); byte_cnt =byte_cnt - 1 9. if pfneb (01h.r7) is low, repeat step (8) 10. if (byte_cnt 1 0) goto step (4) 11. sct (17h.0) ? 1 // status complete trigger 5. 3 .3 ultra dma error handling flag ucrcokb (30h.r3) is used to determine if a crc error event has occurred during latest ultra dma burst. if aucrcen (18h.2) and ascen (18h.5) are both set high, the automatic status complete logic would not be triggered if ucrcokb (30h.r3) is high. therefore, firmware should check ucrcokb (30h.r3) flag after each ultra dma burst. if a crc error has occurred, firmware should set chk (37h.0) to one and manually trigger status complete. 5. 3 .4 ultra dma data-in transfer diagram dmarq(53) dmackb(48) hrdb(50) hwrb(52) iordy(49) dfrdyb(01h.1) data transfer trigger tendb(01h.6) commdnad fifo prefetch tcyc udma burst
w88113c publication release date: mar. 1999 - 85 - revision 0.61 5. 3 .5 data-in transfer flowchart example tendb(01h.6) = 0 tdir(30h.5)=1 data-out transfer end routine dhtack(0eh) = ffh udma & ucrcokb(30h.3) trigger status complete with chk return no yes yes no start hictl(1fh) = 0ch for pio = 08h for mdma = 09h for udma asctrl(18h) = 44h or 74h set twch/l(03h/02h) set tach/l(05h/04h) set tbh/l(25h/24h) adtt(17h.2) = 1 return data-in trigger set mbtc0(12h) set atbhi/lo(35h/34h) fpkt(30h.1)=0 a0 packet transfer end routine yes no cache management
w88113c publication release date: mar. 1999 - 86 - revision 0.61 5. 3 .6 bsy flag control bsy is bit-7 of atapi status register. bsy set bsy clear chip reset set clrbsy (20h.w4) if apkt (30h.r0) is low host reset set drqt (17h.w1) if pio (1fh.2 ) is high set bit srst in atapt device control register host issue atapi command (opcode a0h) if apkten (18h.7) is high set setbsy (20h.w3) if apkt (30h.r0) is low automatic status completion sequence, enabled by sct (17h.w0) or ascen (18h.5) host issues execute diagnostics command (opcode 90h) dfrdyb (01h.r1) becomes low after adtt (17h.w2) is set, if pio (1fh.2 ) is high host issue ata command when drive is selected transfer end if adcen (18h.6) is enabled set adtt (17h.w2) set dsct (17h.w5) if abyen (18h.1) is enabled - lasting 3 system clocks 5. 3 .7 pin hirq control pin hirq (47) is set or clear by the following conditions if the drive is selected and nien is enabled in the atapi device control register. hirq is activated by the following: automatic packet transfer sequence, enabled by apkten (18h.7) automatic status completion sequence, enabled by sct (17h.w0) or ascen (18h.5) write misc0 (2eh) with bit-3 high hirq is de-activated by the following: chip reset or host reset or firmware rest set bit srst in the atapi device control register high host issue ata command while the drive is selected host read atapi status register while the drive is selected write misc0 (2eh) with bit-3 low
w88113c publication release date: mar. 1999 - 87 - revision 0.61 5. 4 decoder logic 5. 4 .1 sync detection/insertion the sync field of cd-rom data is recorded as following: 1 (00h) bytes, 10 (ffh) bytes and 1 (00h) byte. this sync field is detected for sector synchronization if sden (0bh.w6) is enabled. to prevent loss of synchronization caused by broken sync, an internal counter can provide inserted sync signal if sien (0bh.7) is enabled. there are no sync bytes in cd-da format, so sden (0bh.w6) should not be set. 5. 4 .2 descramble bytes 12 to 2351 of each cd-rom sector is scrambled in decoding. setting dscren (0bh.5) high enables the descramble logic. descramble logic should be disabled while reading of cd-da data. 5. 4 .3 disk-monitor mode the decoder logic is in disk-monitor mode if ctrl0 (0ah,w) is set as 80h. in disc-monitor mode, no ecc correction and edc checking is carried. the sector ready interrupt flag srib (01h.r5) is immediately generated when the header bytes are available in head0-3 (04h-07h,r) . the header bytes in disc-monitor mode are less trustworthy than that in buffer-correction mode. 5. 4 .4 parallel ecc correction the error correction encoding/decoding of the cd-rom sector is carried by a reed-solomon product-like code (rspc). the rspc is a product code over gf(2 8 ) field which is generated by the primitive polynomial p(x) = x 8 + x 4 + x 3 + x 2 + 1 the primitive element a of gf(2 8 ) is a = (00000010) where the right-most bit is the least significant bit. the data is divided into high byte plane and low byte plane before decoding. the rspc decoding, operating on bytes, is then applied twice, once to the high byte plane, once to the low byte plane. to improve the efficiency of rspc decoding, a parallel ecc correction logic is implemented on chip. after sync detection and descrambling, the parallel ecc correction is carried on high byte plane and low byte plane simultaneously. this correction scheme is about 33% faster than conventional decoder. the q-code correction and p-code correction are enabled by qcen (0ah.w1) and pcen (0ah.w0) respectively. if both correction operations are enabled, q-code correction is executed first. the corrected data are written back to external ram if cwen (0bh.w4) is high.
w88113c publication release date: mar. 1999 - 88 - revision 0.61 5. 4 .5 edc checking the edc checking logic carry 32-bit crc checking on error corrected data according to its mode. the checking result can be monitored through flag crcok (0ch.r7) . if the result is error, the errors in sector may exceed the capacity of correction logic and some data might be miscorrected. 5. 4 .6 real time edc checking if real time edc checking logic is enabled by setting rtedc (0ah.w6) high, the remainder of serial data is calculated while the sector is being buffered into dram. the sector ready interrupt flag srib (01h.r5) is immediately activated at next sync if the resultant remainder is zero, i.e., no edc error. if there is error, the specified error correction is then applied to the buffered data. this function should not be enabled in disk-monitor mode. 5. 4 .7 decoding sequence model sync dectector descrambler dsp data crcok? repeat correction counter = 0 crcok? edc checker srib(01h.5) = 0 real time edc checker parrllel ecc corrector no yes yes yes no no 5. 4 .8 disc format selection before enable decoder logic through register ctrl0 (0ah,w) , appropriate value should be set to register ctrl1 (0bh.w) according to different disc format. if acen (0ah.w4) and m2rq (0bh.w3) are both high, the type of error correction is automatically determined by form bit in the subheader byte rather than setting of f2rq (0bh.w2) . the value of acen (0ah.w4) does not affect the yellow- book mode-1 correction.
w88113c publication release date: mar. 1999 - 89 - revision 0.61 disc format sien (0bh.7) sden (0bh.6) descren (0bh.5) cwen (0bh.4) m2rq (0bh.3) f2rq (0bh.2) cd-da 1 0 0 0 0 0 yellow book mode 1 1 1 1 1 0 0 yellow book mode 2 1 1 1 0 0 0 cd-rom xa m2f1 1 1 1 1 1 0 cd-rom xa m2f2 1 1 1 x 1 1 5. 4 .9 cd-da data & q-channel extraction there are no sync bytes in cd-da format, so msf bytes of q-channel information can be utilized as synchronization when reading cd-da data. q-channel extraction can be enabled by setting both qen (80h.w5) and scen (2ch.w6) high. once decoder and q-channel extraction are both enabled, the extracted q-channel bytes are written into the dram starting from offset 9e0h of each block regardless of what mode of data is set. the absolute msf information can be retrieved from offset 9e7h, 9e8h and 9e9h of each block. there is an alternative way to access msf of q-channel information. if control bit qmsf (80h.w4) is set high, the corresponding msf bytes in q-channel information would be automatically loaded into head0-2 (04h-06h,r) when each byte is ready from dsp. notice that the value in register head3 (07h,r) and subh0-3 (14h-17h,r) are not available if qmsf (80h.w4) is set high. if q-channel extraction is enabled, device firmware can check flag qcrcok (22h.r4) to see if there is a crc error in the latest q-channel information. smd1 format setting: biah/l (09h/08h) = 000ch ctrlw (10h.w) = 30h sictl1 (2ch,w) = 55h (smd1 mode) qen (80h.w5) = 1 and qmsf (80h.w4) = 1 sdbs (88h.w4) = 1 and sbck (88h.w3) = 1 ctrl1 (0bh.w) = 80h ctrl0 (0ah.w) = 84h scib (01h.r0) substa (22h.r) following the above setting, there is no need to set sictl (21h.w), scbh/l (27h/26h,w) and sctc (5ah,w). in order to transfer the whole sector to host, 2352 bytes, the value in twch/l (03h/02h) should be 0497h and the value in tach/l (05h/04h) should be 0000h.
w88113c publication release date: mar. 1999 - 90 - revision 0.61 5. 4 .10 target search the target search logic is initialized by: (1) setting search limit, (2) setting target and (3) setting targen (80h.w7) high. after the decoding is triggered through ctrl0 (0ah,w), the first sector ready interrupt is generated when: i) the target sector is found, ii) header is larger than target or iii) search limit is reached. if event ii) or iii) occurs, the microprocessor may read out head0-2 (04h- 06,r) to determine the current distance from target. setting lttien (80h.w2) and tnfen (80h.w1) high can generate the associated interrupt flag on srib (01h.r5) before the target is found. decoder_on target(84h-86h) = t - 1 tarctl(80h) = 8fh decoder_ini set tsl(83h) return set bia(09h/08h) set ddb(29h/28h) ctrl1(0bh) = f0h for mode 1 = f8h for mode 2 ctrl0(0ah) = b7h return yes srib(01h.r5) ymonitor_mode? hcei(80h.0) or staerr(80h.6) no no cache management ycache_full? yes decoder_stop return no yes ymonitor_mode? ctrl0(0ah) = 80h no tnfi(80h.1) or ltti(80h.2) yes ymonitor_mode = 0 no ymonitor_mode = 1 decoder_on return yes mask(8ch) = 80h ctrlw(10h) = 50h stop_decoder ctrlw(10h) = 10h return ctrl0(0ah) = 00h 5. 4 .11 automatic header comparison the automatic header comparison logic is enabled by setting targen (80h.w7) and hceen (80h.w0) high. after the first target is found, the value in target (84h-86h) increases from (t - 1) to t . and the decoder is changed from disk-monitor mode to buffer-correction mode. then head0-2 (04h-06h,r) are compare with target (84h-86h) and generate flag hcei (80h.r0) at the end of edc- checking. unless flag staerr (80h.r6) or hcei (80h.r0) is generated, the value in target (84h- 86h) is automatically incremented by one and ready to be compared with next sector. 5. 4 .12 status collection the status collection logic is enabled if any bit in the status-mask-register (8ch-8fh,w) is set high. at the end of edc-checking, flag staerr (80h.r6) becomes high if any status bit error that is enabled by its associating mask bit occurs. the microprocessor can reduce the system overhead by checking staerr (80h.r6) rather than reading out stat (0ch-0fh,r) .
w88113c publication release date: mar. 1999 - 91 - revision 0.61 5. 4 .13 decoder processing flow t-1 t t-2 t+1 t+2 dsp data sector t in block n setor t+1 in block n+1 sector t+2 in block n+2 t+1 buffering decoding target bufen(0ah.2) t ddbh/l (rtc) srib(01h.5) monitor to buffer t-1 n-1 n n+1 t t+1 t+2 note: (n - 1) is the value that set to ddbh/l target is found no interrupt if atmsen(9ah.6)=1 n-1 n n+1 ddbh/l (bic) 5. 4 .14 buffer-independent-correction buffer-independent-correction (bic) is enabled if bicen (9ah.7) is high. in bic mode, the correction is triggered when the sectors not decoded in buffer is larger than one. in bic mode, the ddbh/l (29h/28h) controls the decoding block and increments at the end of edc-checking, except erroneous sectors. meanwhile, the buffering block (internal) increments at each sync. because of the independence of the buffering block and decoding block, the automatic repeat correction can be enabled by setting rclim3-0 (9ch.3-0) the maximum rounds of repeat correction. t t+1 t+2 t+3 t+4 t t+1 t+1 t+2 t+3 t+4 t+5 srib (01h.5) decode buffer crcok (0ch.r7) automatic repeat correction triggered by crc error of sector t+1 in first run 1 2 3 4 5 6 0 1 2 3 4 bbk (internal) ddbh/l (29h/28h)
w88113c publication release date: mar. 1999 - 92 - revision 0.61 5. 4 .15 remove frequent srib & automatic cache management control bit rmsri (5ch.0) should be set when entering buffer mode and be disabled in decoder_off routine. when rmsri (5ch.0) is high, flag srib (01h.r5) is generated only by staerr (80h.r6) , lastbk (80h.r3) or hcei (80h.r0) . so after the target is found and buffer-correction mode is enabled, the first interrupt is generated by lastbk (80h.r3) if there is no decoding error. setting rmsri (5ch.0) high can reduce the overhead of microcontroller while the automatic cache management is used. since the srib (01h.r5) interrupt is removed except for erroneous sectors, the cache management should be implemented through tcc (9dh) . if tcincen (9ch.5) is high, tcc (9dh) increments at the end of edc-checking if there is no staerr (80h.r6) or hcei (80h.r0) error. if acmen (9ch.6) is high, tcc (9dh) decrements at the end of each data-in block transfer. the transfer of working area data should be implemented as linear transfer to prevent error. writing value to skipc (9eh) can be used to implement the cache-partial-hit event. for the cache- miss event, tcc (9dh) should be set 0. the stop of dsp buffering is implemented by following setting ininitialization to prevent buffer wrap- around: bicctl (9ah) ? b0h buflim (9bh) ? cache_limit the following figure shows an example flowchart under following conditions: buffer-independent-correction is enabled remove frequent srib is enabled in buffer mode automatic transfer and cache management is enabled linear address transfer for working area data is enabled in this case, the flag tendb (01h.r6) is generated only when the last block is transferred to host, i.e., ttc (9fh) is zero.
w88113c publication release date: mar. 1999 - 93 - revision 0.61 set tsl(83h) ymonitor_mode = 1 ydec_idle = 0 ctrlw(10h) = 50h bicctl(9ah) = b0h acctl(9ch) = 111xxxxxb tcc(9dh) = 00h set ttc(9fh) read_command cache_check cahce_hit? ydec_idle? set skipc(9eh) no decoder_stop no yes n - 1 = ring_size return yes decoder_restart decoder_restart return decoder_on target(84h-86h) = t - 1 tarctl(80h) = 10xx1111b set bia(09h/08h) ctrl1(0bh) = f0h for mode 1 = f8h for mode 2 ctrl0(0ah) = a7h return yes srib(01h.r5) ymonitor_mode? t - 1 = target(84h-86h) - 1 decoder_stop return ymonitor_mode? ctrl0(0ah) = 80h no tnfi(80h.1) or ltti(80h.2) yes ymonitor_mode = 0 no decoder_on return yes mask(8ch) = 80h decoder_stop ctrlw(10h) = 10h return ctrl0(0ah) = 00h n - 1 = ddb(29h/28h) enctl2(5ch) = 09h return ddb(29h/28h) = n - 1 enctl2(5ch) = 08h no ydec_idle = 1 decoder_on power_on others return decoder_ini return decoder_ini tbh/l(25h/24h) = 00h set hictl(1fh) asctrl(18h) = 74h set twch/l(03h/02h) set tach/l(05h/04h) buflim(9bh) = buf_lim
w88113c publication release date: mar. 1999 - 94 - revision 0.61 5. 5 audio-playback 5. 5 .1 configuration phase 1. configure input/output pin for audio-playback through apcnf (90h). - bit 6: audio playback interrupt enable - bit 4: audio reference clock select - bit 3,2: audio input reference clock setting - bit 1:0: audio data output setting 2. select audio-playback output format through apfmt (91h). after configuration, the pins abck (6) becomes active but data pin keep "mute." 5. 5 .2 playback phase if the desired data sectors are buffered in dram, the following steps can trigger audio playback: 1. set audio-playback start block through apbkh/l (93h/92h). 2. enable audio-playback by setting apen (90h.7) high. 3. wait for interrupt or polling flag apib (01h.r2). 4. if apien (90h.6) is enabled, write apack (97h,w) to deactivate audio-playback-interrupt. 5. if buffer is not empty or end of command, go to step 3. 6. disable audio-playback by setting apen (90h.7) low. the status of playback is directly controlled by the setting of apen (90h.7). so the buffer should be carefully managed to prevent noise or broken song. 5. 5 .3 iec-958 digital audio output the digital output function complies with the iec-958 standard. this function is automatically enabled after configuration of audio playback function. da0en (87h.7) hsts1-0 (2fh.w5-4) arst1-0 (2fh.w3-2) digital audio output pin 1 xxb xxb pin urs (32) default x 01b xxb pin hrstb (21) x xxb 01b pin arstb (60)
w88113c publication release date: mar. 1999 - 95 - revision 0.61 5. 5 .4 audio playback flowchart example play command sctor in buffer set apbkh/l(93h/92h) apen(90h.7) = 1 decoder_restart no yes return apib(01h.2) apack(97h) = ffh last sector in command apen(90h.7) = 0 yes return buffer < threshold & decoder idle no decoder_ini yes no
w88113c publication release date: mar. 1999 - 96 - revision 0.61 6. ordering instruction part no. package w88113cf pqfp 100 W88113CD lqfp 100 7. how to read the top marking example: the top marking of w88113cf inbond w88113cf 904af27039530 1st line: winbond logo 2nd line: the type number: w88113cf 3rd line: tracking code 904 a f 1 7039530 904 : packages made in '99, week 4 a : assembly house id; a means ase, s means spil f : ic revision; d means version d, f means version f 2 : wafers manufactured in winbond fab 2 7039530 : wafer production series lot number
w88113c publication release date: mar. 1999 - 97 - revision 0.61 8. package dimensions w88113cf (100-pin pqfp) 2 1 a h d d e b e h e y a 0.08 0 7 0 0.003 0.05 0.002 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm 7 1.95 0.95 18.15 17.90 0.65 17.65 0.077 0.037 0.951 0.715 0.031 0.941 0.705 0.025 0.931 0.695 0.65 20.10 14.10 0.20 0.40 2.87 20.00 14.00 2.72 19.90 13.90 0.10 0.20 2.57 0.791 0.555 0.008 0.016 0.113 0.787 0.551 0.107 0.026 0.547 0.004 0.008 0.101 0.012 0.006 0.15 0.30 23.65 23.90 24.15 b c d e h d h e l y a a l 1 1 2 e q 0.80 0.783 0.25 0.50 0.010 0.020
w88113c publication release date: mar. 1999 - 98 - revision 0.61 W88113CD (100-pin lqfp) e h e y a a seating plane l l 1 see detail f h d d 1 2 b e c 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.08 0 7 0 0.003 1.00 0.75 16.10 0.60 16.00 0.45 15.90 0.039 0.030 0.870 0.634 0.024 0.866 0.630 0.018 0.862 0.626 0.65 20.10 14.10 0.20 0.38 1.45 20.00 14.00 1.40 19.90 13.90 0.10 0.22 1.35 0.791 0.555 0.008 0.015 0.057 0.787 0.551 0.055 0.026 0.783 0.547 0.004 0.009 0.053 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y q a a l 1 1 2 e 0.013 0.006 0.15 0.32 21.90 22.00 22.10 7 0.020 0.032 0.498 0.802 0.10 0.05 0.002 0.004 0.006 0.15 h e a d q u a r t e r s n o . 4 , c r e a t i o n r d . i i i s c i e n c e - b a s e d i n d u s t r i a l p a r k h s i n c h u , t a i w a n t e l : 8 8 6 - 3 5 - 7 7 0 0 6 6 f a x : 8 8 6 - 3 5 - 7 8 9 4 6 7 w w w : h t t p : / / w w w . w i n b o n d . c o m . t w / t a i p e i o f f i c e 1 1 f , n o . 1 1 5 , s e c . 3 , m i n - s h e n g e a s t r d . t a i p e i , t a i w a n t e l : 8 8 6 - 2 - 7 1 9 0 5 0 5 f a x : 8 8 6 - 2 - 7 1 9 7 5 0 2 t l x : 1 6 4 8 5 w i n t p e w i n b o n d e l e c t r o n i c s ( h . k . ) l t d . r m . 8 0 3 , w o r l d t r a d e s q u a r e , t o w e r i i 1 2 3 h o i b u n r d . , k w u n t o n g k o w l o o n , h o n g k o n g t e l : 8 5 2 - 2 7 5 1 6 0 2 3 - 7 f a x : 8 5 2 - 2 7 5 5 2 0 6 4 w i n b o n d e l e c t r o n i c s ( n o r t h a m e r i c a ) c o r p . 2 7 3 0 o r c h a r d p a r k w a y s a n j o s e , c a 9 5 1 3 4 u . s . a . t e l : 1 - 4 0 8 - 9 4 3 6 6 6 6 f a x : 1 - 4 0 8 - 9 4 3 6 6 6 8 n o t e : a l l d a t a a n d s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t

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